Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.

Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.

Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.

Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.

Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.

Abstract: A proxy-based, nonlinear editing system and method with improved audio level controls is provided. The system includes a proxy file generator, an audio summary file generator that assigns a single audio level for each proxy file video frame, a web user interface having a visual display, and a digital controller. Whenever a proxy file selected for display on the visual display, the digital processor simultaneously provides a graph of the associated audio summary file. The digital processor serially connects, on the same axes, the audio graphs of proxy files being assembled into an edited product, marks the location of audio “spikes”, and provides the web user interface with controls for adjusting the audio level of all or a portion of the audio graphs.

Abstract: A proxy-based, nonlinear editing system and method with improved audio level controls is provided. The system includes a proxy file generator, an audio summary file generator that assigns a single audio level for each proxy file video frame, a web user interface having a visual display, and a digital controller. The audio summary file generator preferably determines the single audio level per video frame by selecting the highest audio level within the frame that lasts long enough to be audibly perceptible. Whenever a proxy file selected for display on the visual display, the digital processor simultaneously provides a graph of the associated audio summary file. The digital processor serially connects, on the same axes, the audio graphs of proxy files being assembled into an edited product, marks the location of audio “spikes”, and provides the web user interface with controls for adjusting the audio level of all or a portion of the audio graphs.

Abstract: A tile rebate cutting apparatus has a guide member, which may be formed by a spirit level, forming a linear guide for a rebate cutting tool, the rebate cutting tool incorporating at least one cutting device, the rebate cutting tool being adapted to engage with said guide member to move along a predetermined line determined by the position of the guide member to enable a cut for a rebate to be made in a ceiling tile.

Abstract: A tile rebate cutting apparatus has a guide member, which may be formed by a spirit level, forming a linear guide for a rebate cutting tool, the rebate cutting tool incorporating at least one cutting device, the rebate cutting tool being adapted to engage with said guide member to move along a predetermined line determined by the position of the guide member to enable a cut for a rebate to be made in a ceiling tile.