Patents by Inventor Daniel R. Baratta

Daniel R. Baratta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Read only memory bitline load-balancing
    Patent number: 8873269
    Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rahul K. Nadkarni, Daniel R. Baratta, Konark Patel, Hoan H. Nguyen
  • READ ONLY MEMORY BITLINE LOAD-BALANCING
    Publication number: 20140268985
    Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Rahul K. Nadkarni, Daniel R. Baratta, Konark Patel, Hoan H. Nguyen