Patents by Inventor Daniel R. Elmhurst
Daniel R. Elmhurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7327605Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: December 28, 2006Date of Patent: February 5, 2008Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
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Patent number: 7177186Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: March 28, 2006Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
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Patent number: 7075822Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: December 31, 2002Date of Patent: July 11, 2006Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
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Patent number: 6809962Abstract: Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.Type: GrantFiled: December 16, 2003Date of Patent: October 26, 2004Assignee: Intel CorporationInventors: Sebastian T. Uribe, Daniel R. Elmhurst
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Publication number: 20040130946Abstract: Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.Type: ApplicationFiled: December 16, 2003Publication date: July 8, 2004Applicant: Intel Corporation, a Delaware corporationInventors: Sebastian T. Uribe, Daniel R. Elmhurst
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Publication number: 20040128594Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
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Patent number: 6747893Abstract: Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.Type: GrantFiled: March 14, 2002Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Sebastian T. Uribe, Daniel R. Elmhurst
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Patent number: 6700820Abstract: Programming non-volatile memory devices includes identifying addresses in a data buffer for storing a particular one of a plurality of threshold voltage levels, then pulsing the array memory cells to program the array memory cells to the particular threshold voltage level. The identifying and pulsing is repeated for each of the threshold voltage levels.Type: GrantFiled: January 3, 2002Date of Patent: March 2, 2004Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Kerry D. Tedrow, Paul D. Ruby
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Publication number: 20030174538Abstract: Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.Type: ApplicationFiled: March 14, 2002Publication date: September 18, 2003Inventors: Sebastian T. Uribe, Daniel R. Elmhurst
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Patent number: 6618287Abstract: A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.Type: GrantFiled: August 29, 2002Date of Patent: September 9, 2003Assignee: Intel CorporationInventor: Daniel R. Elmhurst
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Publication number: 20030123295Abstract: Programming non-volatile memory devices includes identifying addresses in a data buffer for storing a particular one of a plurality of threshold voltage levels, each of which is represented by a unique pattern of signals and then pulsing the array memory cells associated with the identified addresses to program the array memory cells to the particular threshold voltage level. The identifying and pulsing is repeated for each of the threshold voltage levels. Subsequently, each array memory cell is verified as to whether the cell is programmed with a threshold voltage level that correctly represents the corresponding pattern of signals for that cell.Type: ApplicationFiled: January 3, 2002Publication date: July 3, 2003Inventors: Daniel R. Elmhurst, Kerry D. Tedrow, Paul D. Ruby
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Publication number: 20030002339Abstract: A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.Type: ApplicationFiled: August 29, 2002Publication date: January 2, 2003Inventor: Daniel R. Elmhurst
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Patent number: 6480417Abstract: A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.Type: GrantFiled: March 15, 2001Date of Patent: November 12, 2002Assignee: Intel CorporationInventor: Daniel R. Elmhurst
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Publication number: 20020131301Abstract: A memory cell selection scheme that permits simultaneous reading and writing of cells in different memory blocks by using separate routing for bias voltages to the cells. A read path and a program path are used to separately route the read and program voltages to a memory block. Separate read and program transistors are used to selectively route one of those two voltages to a regional voltage line, where individual local voltage transistors can selectively route voltage from the regional voltage line to local voltage lines. By placing a separate set of read and program transistors in each block, each block can be configured to conduct either read or program operations without regard to which of those functions is being performed in other blocks.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Inventor: Daniel R. Elmhurst
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Patent number: 6356062Abstract: A regulator circuit to control the output of a charge pump circuit, to reduce the effects of operating temperature and process variations on available output current from the charge pump circuit. A predetermined fraction of the output voltage of the charge pump circuit is fed back to the input of a differential amplifier, which compares it to a reference voltage. The output of the differential amplifier feeds a voltage controlled oscillator (VCO), which in turn generates a clock signal that is used to drive the charge pump circuit. The normal temperature characteristics of this configuration cause the output of the charge pump circuit to degrade with temperature changes. The regulator circuit can be placed between the differential amplifier and the VCO to adjust the voltage driving the VCO. In one embodiment, a biasing resistor with a negative temperature coefficient can be used in the regulator circuit to offset the normal effects of temperature on the circuit.Type: GrantFiled: September 27, 2000Date of Patent: March 12, 2002Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Binh N. Ngo, Rupinder K. Bains