Patents by Inventor Daniel R. Gaur

Daniel R. Gaur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7929442
    Abstract: Provided are a method, system, and program for managing congestion in a network controller, which in one embodiment, substantially all packets having an assigned priority value below a selected priority level are culled. In another embodiment, selected flows of packets into a network controller are culled at selected culling rates. In one example, a selected flow may be drastically culled. In another example, all flows may be culled at a certain rate which does not exceed a maximum for each flow. In another example, culling techniques may be combined.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Daniel R. Gaur, Linden Cornett
  • Patent number: 7543306
    Abstract: Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of interfacing with the associated device. The device driver periodically monitors usage of the processors in the system and pins a processor to execute the interrupt handler of the device driver based upon the monitored usage. If the usage of the pinned processor exceeds that of one or more of the other processors, the device driver may pin the interrupt handlers to a different, lower utilized processor.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventor: Daniel R. Gaur
  • Patent number: 7286549
    Abstract: Provided are a method, system, and program for processing packets of data. An available packet buffer in memory is allocated to a received packet, wherein the received packet is stored in the allocated packet buffer. A determination is made as to whether a number of available packet buffers is less than a first threshold. A further determination is made as to whether the number of available packet buffers is less than a second threshold if the number of available packet buffers is not less than the first threshold. An operation is initiated to copy the received packet from the allocated packet buffer to a copy buffer if the number of available packet buffers is less than the second threshold.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventor: Daniel R. Gaur
  • Patent number: 7177778
    Abstract: Provided is a method and system for managing data processing rates at a network adapter using a temperature sensor. A temperature of a component in the adapter transmitting data over a network is measured. A rate at which data is processed in the adapter over the network is reduced in response to determining that the measured temperature exceeds a threshold.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Daniel R. Gaur, Patrick L. Connor, Scott P. Dubal
  • Patent number: 7032035
    Abstract: In some embodiments, a method is provided for transmitting packet headers in a network adapter across a network. In this embodiment memory protocol headers and application data into packet buffers are stored on a host. On the network adapter a MAC header storing in a cache. The stored packet buffers and stored MAC header are transmitted across a network thereby reducing DMA requests.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventor: Daniel R. Gaur
  • Patent number: 6968411
    Abstract: An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, implement interrupt processing in an efficient, parallel manner that reduces average interrupt latency. In one embodiment, the apparatus may include an interrupt receiver coupled to a plurality of interrupt handlers which respond to uniquely identified interrupting events. Responses may occur in an overlapping fashion in a multi-threaded environment. The system may include a processor coupled to a local memory and an interrupt receiver. Interrupt handlers, which may be coupled to the interrupt receiver, process uniquely identified interrupts. The method may include receiving multiple interrupts and executing corresponding interrupt handlers scheduled in response to receipt of the interrupts, with each handler being uniquely adapted to service a particular interrupting event.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: November 22, 2005
    Assignee: Intel Corporation
    Inventors: Daniel R. Gaur, Patrick L. Connor
  • Publication number: 20040085977
    Abstract: Provided are a method, system, and program for processing packets of data. An available packet buffer in memory is allocated to a received packet, wherein the received packet is stored in the allocated packet buffer. A determination is made as to whether a number of available packet buffers is less than a first threshold. A further determination is made as to whether the number of available packet buffers is less than a second threshold if the number of available packet buffers is not less than the first threshold. An operation is initiated to copy the received packet from the allocated packet buffer to a copy buffer if the number of available packet buffers is less than the second threshold.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: Intel Corporation
    Inventor: Daniel R. Gaur
  • Publication number: 20030189945
    Abstract: An arrangement is provided for selective completion indication of controller events. Data to be transmitted is read and transmitted upon receiving a request for transmission. A completion indication assiciated with the status of the transmission is returned only when a request for the completion indication is received.
    Type: Application
    Filed: April 5, 2002
    Publication date: October 9, 2003
    Inventors: Patrick L. Connor, Daniel R. Gaur
  • Publication number: 20030182484
    Abstract: An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, implement interrupt processing in an efficient, parallel manner that reduces average interrupt latency. In one embodiment, the apparatus may include an interrupt receiver coupled to a plurality of interrupt handlers which respond to uniquely identified interrupting events. Responses may occur in an overlapping fashion in a multi-threaded environment. The system may include a processor coupled to a local memory and an interrupt receiver. Interrupt handlers, which may be coupled to the interrupt receiver, process uniquely identified interrupts. The method may include receiving multiple interrupts and executing corresponding interrupt handlers scheduled in response to receipt of the interrupts, with each handler being uniquely adapted to service a particular interrupting event.
    Type: Application
    Filed: March 19, 2002
    Publication date: September 25, 2003
    Applicant: Intel Corporation
    Inventors: Daniel R. Gaur, Patrick L. Connor
  • Patent number: 6618814
    Abstract: A method for determining if a cable is present at a network connection, and adjusting a power signal to the network connection depending upon whether or not a cable is present is disclosed.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Daniel R. Gaur, Timothy E. W. Labatte, David L. Chalupsky
  • Publication number: 20030145097
    Abstract: An arrangement is provided for ingress throttling via adaptive interrupt delay scheduling. When packets are received, a receive interrupt is issued with a delay determined based on the backlog information of an associated host, gathered from the number of packets returned from the host after the completion of processing previously delivered packets.
    Type: Application
    Filed: January 28, 2002
    Publication date: July 31, 2003
    Inventors: Patrick L. Connor, Daniel R. Gaur, Eric K. Mann, Gary Y. Tsao, Michael C. Gibson
  • Publication number: 20020188749
    Abstract: Systems and methods for dynamically tuning the interrupt delay of a network adapter in response to variations in incoming network traffic loads. As incoming network traffic loads increase, the interrupt delay may be increased to permit an interrupt handler to “clean up” a greater number of packets with a single interrupt. Conversely, as incoming network traffic loads decrease, the interrupt delay may be decreased to expedite execution of the interrupt handler to “clean up” received packets. By monitoring incoming network traffic conditions, the duration of the interrupt delay of the network adapter can be optimized to efficiently receive incoming packets without excessive processor utilization and without poor response latency.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 12, 2002
    Inventor: Daniel R. Gaur
  • Publication number: 20020144004
    Abstract: A driver having an interrupt service routine including an interrupt handler and at least two deferred procedure calls. Each of the at least two deferred procedure calls is associated with a particular interrupt event or type of interrupt event. If multiple interrupt events occur, the interrupt events may be concurrently processed on separate deferred procedure calls, resulting in a substantially reduced interrupt handling latency.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventors: Daniel R. Gaur, Patrick L. Connor, Lucas M. Jenison, Patrick J. Luhmann, Linden Minnick
  • Publication number: 20020073216
    Abstract: In some embodiments, a method is provided for transmitting packet headers in a network adapter across a network. In this embodiment memory protocol headers and application data into packet buffers are stored on a host. On the network adapter a MAC header storing in a cache. The stored packet buffers and stored MAC header are transmitted across a network thereby reducing DMA requests.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventor: Daniel R. Gaur