Abstract: The present invention relates to the method of and apparatus for performing test operations on a primary counter to make sure that it is continually providing correct operational capability. The tests comprise periodically interrupting the operation of the primary counter, forcing it to count to both the maximum and minimum limits and checking to make sure that the limit has been obtained, inserting an intermediate number and checking to be sure that this number can be transferred therethrough and then resetting the primary counter to the count of a backup counter which has been keeping count during the test process. Finally, a comparison is continually provided during normal operation between the backup and the primary counter to make sure that they are tracking with the same counts. Failure of any of the comparisons or tests to be completed in accordance with specified results causes an error signal to be generated as an alarm.

Abstract: A method of and circuitry for the operations of reading from and writing into a memory, each of which operations occurs on a sequential basis and each of which has different clock rates while preventing erroneous information from being read due to interference with attempted writing at the same address. This is accomplished by comparing the read and write addresses and when they approach each other, forcing the most significant bit of one of the sequentially occurring addresses to be altered in a step function whereby interference cannot occur. The above is used as an elastic store.

Abstract: The method and circuitry for detecting two different binary numbers or digital words in a register or counter using logic gates wherein bits are detected using n-1 logic gates when all the digits of each of words or numbers are at the same one of a plurality of possible logic levels. In other words, two numbers such as all logic ones as the first number and all logic zeros as the second number. Specifically, this concept is applied to checking an up-down counter output so that it is prevented from overflowing or underflowing by stopping it at either a count of all logic zeros or all logic ones.