Patents by Inventor Daniel R. Vinot

Daniel R. Vinot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4611276
    Abstract: A control logic circuit (C) is provided in each unit such as processors and emories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.
    Type: Grant
    Filed: March 20, 1984
    Date of Patent: September 9, 1986
    Assignee: Compagnie Internationale pour l'Informatique CII-Honeywell Bull
    Inventor: Daniel R. Vinot
  • Patent number: 4472771
    Abstract: A central sub-system of a data processing system, including an operator console controlling a service processor, is divided into several sub-units, functioning separately from each other. The sub-units include processors that are connected together and to a common controller for a common memory unit by data, address and control buses. Each sub-unit includes a configuration device that stores an appurtenance indicator derived from the service processor in response to sub-unit initialization, and enables its associated sub-unit to exchange data with the memory unit. The sub-unit having the highest priority of the sub-units attempting to access the memory units is connected to the memory unit by the controller. A single configuration memory stores an indication of the sub-units in service in the central sub-system. The configuration memory is addressed each time the memory unit is addressed by a signal indicative of the appurtenance indicator derived from the selected sub-unit.
    Type: Grant
    Filed: November 13, 1980
    Date of Patent: September 18, 1984
    Assignee: Compagnie Internationale pour l'Informatique CII Honeywell Bull (Societe Anonyme)
    Inventors: Jacques M. J. Bienvenu, Pierre G. Antoine, Robert J. A. Bavoux, Daniel R. Vinot
  • Patent number: 4433375
    Abstract: A control logic circuit (C) is provided in each unit such as processors and memories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission bus only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.
    Type: Grant
    Filed: November 25, 1980
    Date of Patent: February 21, 1984
    Assignee: Compagnie Internationale pour l'Informatique CII-Honeywell Bull (Societe Anonyme)
    Inventor: Daniel R. Vinot