Abstract: An integrated circuit including embedded test functionality. An integrated circuit may include a plurality of processor cores each configured to execute instructions, and a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of the circuits. The test access port may include virtualization logic configured to allow a first set of instructions executing on the given processor core to control activity of the test access port for testing of the circuits. In one embodiment, the circuits may be accessible for testing via a plurality of scan chains, wherein the scan chains and the test access port are compliant with a version of Joint Test Access Group (JTAG) standard IEEE 1149, and wherein the test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

Abstract: A settop box system for capturing and controlling live and recorded audio and video content. The system records digital and analog data from video and audio content, such as in a home entertainment center. The system records data from the content as specified and the data may be sequenced into clips that can be searched and indexed. A user may create comparison programs that allow searches of either pre-recorded or incoming content to be performed. In addition, the program allows editing of recorded programs, such as filtering of audio content or overlaying a video program with a different audio background. Multiple audio and video feeds may be handled simultaneously and the program's functions may be executed without viewing of the content being manipulated. The recorded content may also be indexed and even clips of the content may be indexed.

Abstract: A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.

Abstract: The present invention provides an integrated circuit (IC). In one embodiment, the IC includes a substrate and a plurality of gate array blocks located on the substrate. Each of the blocks includes a programmable gate array (PGA) containing at least a portion of a circuit design in an interconnect layer thereof, and a field-programmable gate array (FPGA) coupled to the PGA and capable of containing a configuration that augments the portion of the circuit design. In this embodiment, the PGA and the FPGA cooperate to effect the circuit design. In another aspect, the present invention provides a method of designing an IC. In yet another aspect, the present invention provides a method of manufacturing ICs.

Abstract: An apparatus and method for using the apparatus for reducing analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing the integrated circuit and means for accelerating circuit analysis using the integrated logic analyzer. The means may be selected from the group consisting of a high speed sampling circuit coupled to the integrated logic analyzer and an on-board circuit testing and analysis apparatus including the integrated logic analyzer. Use of the apparatus enables lower production costs by speeding up circuit analysis as well as providing analysis of high speed circuits in a cost effective manner.

Abstract: A method implements a change to a circuit design for a system formed on a semiconductor chip, the circuit design including at least one circuit core. The method includes providing in the circuit design at least one field programmable gate array (FPGA) core, extracting an incremental change to the circuit design by comparing a new resister-transfer-level (RTL) design and an old RTL design for the system, synthesizing the incremental change into a netlist for the at least one FPGA core, generating new metal layer interconnections so as to provide an input and an output for the at least one FPGA core in accordance with the incremental change, and programming the at least one FPGA core in accordance with the netlist. The at least one FPGA core is provided in an otherwise unused area of the chip.

Abstract: A settop box system for capturing and controlling live and recorded audio and video content. The system records digital and analog data from video and audio content, such as in a home entertainment center. The system records data from the content as specified and the data may be sequenced into clips that can be searched and indexed. A user may create comparison programs that allow searches of either pre-recorded or incoming content to be performed. In addition, the program allows editing of recorded programs, such as filtering of audio content or overlaying a video program with a different audio background. Multiple audio and video feeds may be handled simultaneously and the program's functions may be executed without viewing of the content being manipulated. The recorded content may also be indexed and even clips of the content may be indexed.

Abstract: A tool and method for increasing fault coverage of an integrated circuit. The tool includes a key nodes detection device for matching key nodes to a fault grading report list of undetected nodes, a multi-sites selection device for reading a layout file of available multi unit sites for the integrated circuit, a site matching device for matching available multi-unit sites to key undetected nodes, and a netlist generation device for building logic functions in the available multi-unit sites for connection to the key undetected nodes. Use of the invention enables increased fault coverage of integrated circuit circuits for little or no added expense.

Abstract: A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.

Abstract: A speech recognition remote control unit (SR RCU) having the ability to leverage the advanced processing and memory capabilities of a settop box in order to provide enhanced SR capability and enhanced user control of components in an audio-video system. Programming of commands takes place in either the SR RCU or in the settop box, or both. Commands programmed into the settop box may be initiated by speech communications received by the SR RCU that are then sent to the settop box via wireless transfer. The initiated commands may further be sent to a device either directly from the settop box, or via relay from the settop box to the SR RCU, and then to the device. The SR RCU may be capable of receiving both speech communications and wireless information.

Abstract: A circuit generally comprising a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.

Abstract: A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.

Abstract: An apparatus and method for using the apparatus for reducing analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing the integrated circuit and means for accelerating circuit analysis using the integrated logic analyzer. The means may be selected from the group consisting of a high speed sampling circuit coupled to the integrated logic analyzer and an on-board circuit testing and analysis apparatus including the integrated logic analyzer. Use of the apparatus enables lower production costs by speeding up circuit analysis as well as providing analysis of high speed circuits in a cost effective manner.

Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations.

Abstract: A bitstream management system and method which provides an infrastructure to enable comprehensive testing of devices that implement multiple syntax rule sets. In this system and method, modules for the individual syntax rule sets are implemented using profiles (concise representations of data streams). The modules each have a profile generator which determines a permutation of selected values for a set of syntax variables and translates that permutation into a profile. The modules also each have a data stream generator which converts the profiles into the data streams they represent. The use of profiles provides an advantageous method for maintaining the modularity of the syntax modules when integrating them together to provide a system for generating data streams which must comply with multiple syntax rule sets.

Abstract: A system for interactive design and simulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time. The user is further able to view any information relevant to any object in the design at any level of design abstraction, and is able to view multiple levels of design abstraction simultaneously and to display information common to the various representations.

Abstract: A system for designing an integrated circuit with multiple functions is disclosed. The system creates a set of files defining a structure for a plurality of functions existing within one integrated circuit. Floorplanning modifications are then permissible within any functional block, as well as from one functional block to another since the files for each integrated circuit chip are reconfigureable upon modification. The subject invention also provides for floorplanning modifications involving multiple integrated circuit chips wherein any one functional block may be moved from one integrated circuit chip to another to achieve better optimization with less restrictions.

Abstract: In an electronic design automation (EDA) system, various models are simulated and interfaced to certain target systems, logic analyzers, modeler, functional testers, emulators, hardware accelerators, hardware modelers, or other simulators. An add-on circuit card connects the simulator to the external systems. A computer program controls simulation start, stop, single-stepping, polling, interrupting and signal monitoring. The software program includes a model input/ouput file, a model input/output parcer, a configuration module, an address generation module, a run-time module, and a C-language module.

Abstract: A system for interactive design and simulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time. The user is further able to view any information relevant to any object in the design at any level of design abstraction, and is able to view multiple levels of design abstraction simultaneously and to display information common to the various representations.

Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations.