Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

Abstract: Liquid filter assemblies, features, components and methods are described. In general, a liquid filter cartridge is provided which includes features that help ensure that when the assembly is serviced, the cartridge positioned within the assembly is a proper one, in proper sealing orientation, for appropriate use. Features that can be used to provide for this include: a seal on the filter cartridge that defines a seal pattern non-orthogonal to a plane perpendicular to a central axis of the filter cartridge; and, a member of a projection/receiver arrangement on the filter cartridge which is orientated to engage a portion of a liquid filter assembly, for example a liquid flow collar, to allow sealing when the cartridge is a properly positioned cartridge and a properly configured cartridge. Assembly features are described. Also, a flexible radial projection arrangement providing snap-fit interaction between a cartridge and housing is provided. Methods of assembly and use as described.

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: Instruction set architecture extensions to configure priority ordering of divergent target branch instructions on SIMT computing platforms to enable tools such as compilers (e.g., under influence of execution profilers) or human software developers to configure branch direction prioritization explicitly in code. Extensions for simple (two-way) branch instructions as well as multi-target (more than two branch target instructions) are disclosed.

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

Abstract: A method of in situ ultrasonic flow meter validation includes receiving data characterizing first signal diagnostics and data characterizing a first speed of a first acoustic signal through a gas mixture along a first path in a pipe. The first speed of the first acoustic signal is detected by a first channel of an ultrasonic flow meter including a first pair of transducers that are separated by a first path length of the first path. The gas mixture is configured to flow along a flow path in the pipe. The method also includes determining a status associated with the ultrasonic flow meter based on the data characterizing the first signal diagnostics and/or a difference between the first speed of the first acoustic signal and an independently calculated speed of sound. The speed of sound is calculated based on one or more properties of the gas mixture.

Abstract: A system for flare combustion control includes a sound speed measurement device for measuring sound speed in a flare vent gas, and a flare combustion controller including a memory and a processor. The processor is configured to receive the measured sound speed and determine, based on the measured sound speed, a molecular weight of the flare vent gas. The processor is further configured to determine, based on the determined molecular weight, a net heating value of the flare vent gas, and adjust the net heating value of the flare vent gas by regulating an amount of a supplemental fuel gas in the flare vent gas.

Abstract: A system for flare combustion control includes a sound speed measurement device for measuring sound speed in a flare vent gas, and a flare combustion controller including a memory and a processor. The processor is configured to receive the measured sound speed and determine, based on the measured sound speed, a molecular weight of the flare vent gas. The processor is further configured to determine, based on the determined molecular weight, a net heating value of the flare vent gas, and adjust the net heating value of the flare vent gas by regulating an amount of a supplemental fuel gas in the flare vent gas.

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

Abstract: A patch memory system for accessing patches from a memory is disclosed. A patch is an abstraction that refers to a contiguous, array of data that is a subset of an N-dimensional array of data. The patch memory system includes a tile cache, and is configured to fetch data associated with a patch by determining one or more tiles associated with an N-dimensional array of data corresponding to the patch, and loading data for the one or more tiles from the memory into the tile cache. The N-dimensional array of data may be a two-dimensional (2D) digital image comprising a plurality of pixels. A patch of the 2D digital image may refer to a 2D subset of the image.

Abstract: A system for flare combustion control includes a sound speed measurement device for measuring sound speed in a flare vent gas, and a flare combustion controller including a memory and a processor. The processor is configured to receive the measured sound speed and determine, based on the measured sound speed, a molecular weight of the flare vent gas. The processor is further configured to determine, based on the determined molecular weight, a net heating value of the flare vent gas, and adjust the net heating value of the flare vent gas by regulating an amount of a supplemental fuel gas in the flare vent gas.

Abstract: A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

Abstract: A patch memory system for accessing patches from a memory is disclosed. A patch is an abstraction that refers to a contiguous, array of data that is a subset of an N-dimensional array of data. The patch memory system includes a tile cache, and is configured to fetch data associated with a patch by determining one or more tiles associated with an N-dimensional array of data corresponding to the patch, and loading data for the one or more tiles from the memory into the tile cache. The N-dimensional array of data may be a two-dimensional (2D) digital image comprising a plurality of pixels. A patch of the 2D digital image may refer to a 2D subset of the image.

Abstract: A system, method, and computer program product are provided for providing prioritized access for multithreaded processing. The method includes the steps of allocating threads to process a workload and assigning a set of priority tokens to at least a portion of the threads. Access to a resource, by each one of the threads, is based on the priority token assigned to the thread and the threads are executed by a multithreaded processor to process the workload.

Abstract: Embodiments of apparatuses and risers for reacting a feedstock in the presence of a catalyst and methods for installing a baffle in such risers are provided. In one example, a riser comprises a sidewall that defines a cylindrical housing surrounding an interior. A plurality of baffle assemblies is releasably coupled to the sidewall and each comprises a baffle section. The baffle sections together define a segmented baffle ring extending inwardly in the interior.

Abstract: A system, method, and computer program product are provided for providing prioritized access for multithreaded processing. The method includes the steps of allocating threads to process a workload and assigning a set of priority tokens to at least a portion of the threads. Access to a resource, by each one of the threads, is based on the priority token assigned to the thread and the threads are executed by a multithreaded processor to process the workload.

Abstract: Embodiments of apparatuses and risers for reacting a feedstock in the presence of a catalyst and methods for installing a baffle in such risers are provided. In one example, a riser comprises a sidewall that defines a cylindrical housing surrounding an interior. A plurality of baffle assemblies is releasably coupled to the sidewall and each comprises a baffle section. The baffle sections together define a segmented baffle ring extending inwardly in the interior.