Abstract: A method is provided that includes reading data in a storage medium, detecting, during the reading of the data in the storage medium, by a controller a change in an encryption/decryption scheme used to read and write the data in the storage medium, in response to detecting the change in encryption/decryption scheme in the data, causing, by the controller, a logical block address to return an indication of being written in zeros when a physical block address associated with the logical block address encrypted using an first encryption/decryption scheme, and causing, by the controller, a write channel to write zeroes using a second encryption/decryption scheme to the physical block address.

Abstract: A method is provided that includes reading data in a storage medium, detecting, during the reading of the data in the storage medium, by a controller a change in an encryption/decryption scheme used to read and write the data in the storage medium, in response to detecting the change in encryption/decryption scheme in the data, causing, by the controller, a logical block address to return an indication of being written in zeros when a physical block address associated with the logical block address encrypted using an first encryption/decryption scheme, and causing, by the controller, a write channel to write zeroes using a second encryption/decryption scheme to the physical block address.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device is provided that includes a memory location configured to store information representing data written using a first encryption/decryption method, a read channel configured to read and decrypt information using a second encryption/decryption method and an apparatus configured to prevent the read channel from reading the memory location using the second encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written is disclosed. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of a predefined or custom code is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A storage device may include a data storage portion, including a plurality of blocks of data, and a controller. The controller may be configured to receive a command that includes an inherent trim request for the plurality of blocks of data. The controller may be configured to perform a trim operation on a first set of trim blocks from the plurality of blocks of data, which may include fewer than all blocks of the plurality of blocks of data and may include trim blocks on which the controller can complete the trim operation within a predetermined time. The controller may be configured to update a pending trim table to include an indication of a second set of trim blocks on which trim is to be performed, which may include blocks of data on which the controller cannot complete the trim operation within the predetermined time.

Abstract: A storage device may include a data storage portion, including a plurality of blocks of data, and a controller. The controller may be configured to receive a command that includes an inherent trim request for the plurality of blocks of data. The controller may be configured to perform a trim operation on a first set of trim blocks from the plurality of blocks of data, which may include fewer than all blocks of the plurality of blocks of data and may include trim blocks on which the controller can complete the trim operation within a predetermined time. The controller may be configured to update a pending trim table to include an indication of a second set of trim blocks on which trim is to be performed, which may include blocks of data on which the controller cannot complete the trim operation within the predetermined time.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written is disclosed. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of a predefined or custom code is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Abstract: A method, apparatus, and program product access memory resources of a computer using a group of direct access memory (DMA) devices. A first DMA device is designated a primary device after association with an active translation table (ATT), while a second DMA device is designated a backup device after association with an inactive translation table (ITT). A translation is entered into the ATT for the first DMA device to permit it to perform a DMA operation, while a translation is inhibited from being entered into the ITT for a second DMA device to prevent it from performing a DMA operation. Thereafter, the roles of the first and second DMA devices may be swapped by associating the first DMA device with the ITT and associating the second DMA device with the ATT. The computer may be a logically partitioned computer of the type that includes a plurality of logical partitions.

Abstract: A method, apparatus, and program product access memory resources of a computer using a group of direct access memory (DMA) devices. A first DMA device is designated a primary device after association with an active translation table (ATT), while a second DMA device is designated a backup device after association with an inactive translation table (ITT). A translation is entered into the ATT for the first DMA device to permit it to perform a DMA operation, while a translation is inhibited from being entered into the ITT for a second DMA device to prevent it from performing a DMA operation. Thereafter, the roles of the first and second DMA devices may be swapped by associating the first DMA device with the ITT and associating the second DMA device with the ATT. The computer may be a logically partitioned computer of the type that includes a plurality of logical partitions.

Abstract: A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation.