Abstract: The technology relates to partially redundant equipment architectures for vehicles able to operate in an autonomous driving mode. Aspects of the technology employ fallback configurations, such as two or more fallback sensor configurations that provide some minimum amount of field of view (FOV) around the vehicle. For instance, different sensor arrangements are logically associated with different operating domains of the vehicle. Fallback configurations for computing resources and/or power resources are also provided. Each fallback configuration may have different reasons for being triggered, and may result in different types of fallback modes of operation. Triggering conditions may relate, e.g., to a type of failure, fault or other reduction in component capability, the current driving mode, environmental conditions in the vicinity of vehicle or along a planned route, or other factors.

Abstract: One example system for preventing data loss during memory blackout events comprises a memory device, a sensor, and a controller operably coupled to the memory device and the sensor. The controller is configured to perform one or more operations that coordinate at least one memory blackout event of the memory device and at least one data transmission of the sensor.

Abstract: The technology relates to partially redundant equipment architectures for vehicles able to operate in an autonomous driving mode. Aspects of the technology employ fallback configurations, such as two or more fallback sensor configurations that provide some minimum amount of field of view (FOV) around the vehicle. For instance, different sensor arrangements are logically associated with different operating domains of the vehicle. Fallback configurations for computing resources and/or power resources are also provided. Each fallback configuration may have different reasons for being triggered, and may result in different types of fallback modes of operation. Triggering conditions may relate, e.g., to a type of failure, fault or other reduction in component capability, the current driving mode, environmental conditions in the vicinity of vehicle or along a planned route, or other factors.

Abstract: The technology relates to partially redundant equipment architectures for vehicles able to operate in an autonomous driving mode. Aspects of the technology employ fallback configurations, such as two or more fallback sensor configurations that provide some minimum amount of field of view (FOV) around the vehicle. For instance, different sensor arrangements are logically associated with different operating domains of the vehicle. Fallback configurations for computing resources and/or power resources are also provided. Each fallback configuration may have different reasons for being triggered, and may result in different types of fallback modes of operation. Triggering conditions may relate, e.g., to a type of failure, fault or other reduction in component capability, the current driving mode, environmental conditions in the vicinity of vehicle or along a planned route, or other factors.

Abstract: A circuit for performing computations for a neural network comprising multiple neural network (NN) layers. The circuit includes a processing device that provides programming data for performing the computations and a core in data communication with the processing device to receive the programming data. The core includes activation memory that stores inputs for a layer and parameter memory that stores parameters for a first NN layer. The core also includes a rotation unit that rotates accessing the inputs from the activation memory based on the programming data and a computation unit that receives a respective input and a parameter for the first NN layer and generates an output of the first NN layer using the input and the parameter. The core also includes a crossbar unit that causes the output to be stored, in the activation memory, in accordance with a bank assignment pattern.

Abstract: The technology relates to partially redundant equipment architectures for vehicles able to operate in an autonomous driving mode. Aspects of the technology employ fallback configurations, such as two or more fallback sensor configurations that provide some minimum amount of field of view (FOV) around the vehicle. For instance, different sensor arrangements are logically associated with different operating domains of the vehicle. Fallback configurations for computing resources and/or power resources are also provided. Each fallback configuration may have different reasons for being triggered, and may result in different types of fallback modes of operation. Triggering conditions may relate, e.g., to a type of failure, fault or other reduction in component capability, the current driving mode, environmental conditions in the vicinity of vehicle or along a planned route, or other factors.

Abstract: The technology provides for a system and method to secure a processing device in a socket in high shock and vibration environments, such as inside a vehicle. The processing device may be fitted in the socket, which may be soldered on a circuit board. A mounting plate may be attached to the circuit board. The processing device may be arranged between the circuit board and the mounting plate such that the processing device may be secured to the socket by a compression force applied by the mounting plate. The mounting plate may further provide cooling for the processing device.

Abstract: A system and method for low latency and higher bandwidth communication between a central processing unit (CPU) and an accelerator is disclosed. When the CPU updates a copy of data stored at a shared memory, the CPU also sends an “invalidate” command to a cache coherent interconnect (CCI). The CCI forwards the invalidate command to a dedicated cache register (DCR). The DCR marks its copy of the data as “out-of-date” and requests an up-to-date copy of the data from the CCI. The CCI then retrieves up-to-date data for the DCR. When the DCR receives the up-to-date data from the CCI, the DCR replaces the out-of-date data with the up-to-date data, and marks the up-to-date data with the status of “valid.” The DCR can then provide data to an accelerator with a status of “out-of-date” or “valid.

Abstract: A system and method for low latency and higher bandwidth communication between a central processing unit (CPU) and an accelerator is disclosed. When the CPU updates a copy of data stored at a shared memory, the CPU also sends an “invalidate” command to a cache coherent interconnect (CCI). The CCI forwards the invalidate command to a dedicated cache register (DCR). The DCR marks its copy of the data as “out-of-date” and requests an up-to-date copy of the data from the CCI. The CCI then retrieves up-to-date data for the DCR. When the DCR receives the up-to-date data from the CCI, the DCR replaces the out-of-date data with the up-to-date data, and marks the up-to-date data with the status of “valid.” The DCR can then provide data to an accelerator with a status of “out-of-date” or “valid.

Abstract: Disclosed method, system and computer readable storage medium embodiments for providing hardware-efficient universal hashing functions include performing a first hash function on a received input key or a bit sequence derived from the received input key to generate a hashed input key, selecting a plurality of input key portions from the hashed input key, accessing, a respective permutation table for each of the input key portions from a group of permutation tables to generate a permuted key portion, and combining at least the generated permuted key portions to form a hash value.

Abstract: Disclosed method, system and computer readable storage medium embodiments for providing hardware-efficient universal hashing functions include performing a first hash function on a received input key or a bit sequence derived from the received input key to generate a hashed input key, selecting a plurality of input key portions from the hashed input key, accessing, a respective permutation table for each of the input key portions from a group of permutation tables to generate a permuted key portion, and combining at least the generated permuted key portions to form a hash value.

Abstract: A method and apparatus for selecting a queue for service across a shared link. The method includes determining a priority for each queue (202) within a plurality of ingresses (102), wherein the priority is instantaneous for a given timeslot for data transfer, selecting a queue having a first priority for each group of queues within each ingress (104) having packets destined for a particular egress (104), selecting a queue having a second priority for each subset of queues having first priorities and having packets destined for the particular egress (104), and selecting the queue having the second priority for service across the shared link in the given timeslot.

Abstract: A scheduling approach enables scheduling sequential execution of rules in a single cycle of a synchronous system without necessarily requiring explicit implementation of a composite rule for each sequence of rules than may be composed. One method for designing a synchronous digital system includes using modules with multiple successive interfaces such that within the a single clocked cycle, each module performs a function equivalent to completing interactions through one of its interfaces before performing interactions through any succeeding one of its interfaces. The scheduled state transition rules are associated with corresponding interfaces of the modules.