Abstract: A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including address, data, opcodes, and various flags registers that are used by other subsystems including the program buffer, burst read module, register block, and microcontroller. In addition, the command decoder contains clock synchronization logic, controls the sleep function of the microcontroller and serves as a test mode controller.

Abstract: Some embodiments includes a digital control system having a microcontroller to handle a first command associated with a first operation of a memory device, and circuitry coupled to the microcontroller to handle a second command associated with a second operation of the memory device without involving the microcontroller in the second operation.

Abstract: A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.

Abstract: A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.

Abstract: A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.

Abstract: An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data bus. When operating as a receiver, the interface receives signals from the parallel data bus and restores the original signals which were combined and compressed. The device interface modes are selectable to be compatible in different device and circuit configurations.

Abstract: A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2M possible data values for a group of M data bits uniquely corresponds to one of 2M distinct pulse widths. This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.

Abstract: A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.

Abstract: A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.

Abstract: An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.

Abstract: A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and inputting the delayed outputs and the non-delayed signal into AND logic gates, whose outputs are used to clock flip-flop registers. The registers are reset to a known state at the start of each signal pulse and toggled to an opposite state if clocked. The registered outputs are interpreted by logic to obtain the corresponding M-bit groups.

Abstract: A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and using the delayed outputs to clock flip-flop registers to sample the non-delayed signal. The registered output is interpreted by logic gates to obtain the corresponding M-bit groups. The decoder circuit may have two substantially identical pulse width determining blocks, one receiving the DPPM signal for measuring high pulses, and the other receiving an inverted DPPM signal for measuring the low pulses.