Patents by Inventor Daniel S. Dean

Daniel S. Dean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6256242
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a VCC-to-ground voltage drop for the entire refresh interval.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Daniel S. Dean