Abstract: An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

Abstract: An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a wafer, and the chiplets have interconnections to wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The wafer has at least one wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the wafer circuit to the chiplet circuit.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, and a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. First chiplets have a first thickness and backsides bonded directly to first portions of the areas of the top surface of the backside capping layer. Second chiplets have a second, thinner thickness and backsides bonded to second portions of the areas of the top surface of the backside capping layer. The backside of the second chiplets are directly bonded to metal backfill plugs of at second portions of the backside capping layer. A lateral bonding material bonds side surfaces of the first chiplets, the second chiplets and the plugs to side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: Methods and compositions are disclosed for treating a subject with a cancer. The compositions can include a chimeric molecule comprising an agent that specifically binds the interleukin 4 receptor (IL-4R) and a toxic moiety, an interferon alpha (IFN?), and an interferon gamma (IFN?). In some non-liming embodiments, the compositions can also include monocytes. The methods disclosed herein include administering a therapeutically effective amount of the compositions taught herein to a subject with cancer, thereby treating the cancer in the subject, wherein cells in the cancer express IL-4R. In some non-liming embodiments, the methods can also include administering monocytes.

Abstract: Methods and compositions are disclosed for treating a subject with a cancer. The compositions can include a chimeric molecule comprising an agent that specifically binds the interleukin 4 receptor (IL-4R) and a toxic moiety, an interferon alpha (IFN?), and an interferon gamma (IFN?). In some non-liming embodiments, the compositions can also include monocytes. The methods disclosed herein include administering a therapeutically effective amount of the compositions taught herein to a subject with cancer, thereby treating the cancer in the subject, wherein cells in the cancer express IL-4R. In some non-liming embodiments, the methods can also include administering monocytes.

Abstract: Methods for integrating transition metal oxide (TMO) layers into a compound semiconductor device structure via selective oxidation of transition metal nitride (TMN) layers within the structure.

Abstract: Methods for integrating transition metal oxide (TMO) layers into a compound semiconductor device structure via selective oxidation of transition metal nitride (TMN) layers within the structure.