Abstract: Application servers having multiple virtual machines are restarted by sequentially addressing each active virtual machine (VM) by adding a corresponding new VM prior to stopping the active VM before adding another new VM corresponding to another of the multiple virtual machines to be restarted. Application servers are monitored for restart conditions that trigger a sequential process of adding a new VM and stopping the corresponding active VM.

Abstract: Application servers having multiple virtual machines are restarted by sequentially addressing each active virtual machine (VM) by adding a corresponding new VM prior to stopping the active VM before adding another new VM corresponding to another of the multiple virtual machines to be restarted. Application servers are monitored for restart conditions that trigger a sequential process of adding a new VM and stopping the corresponding active VM.

Abstract: A method and information processing system facilitate debugging of a multi-threaded application. A control program request associated with at least one thread of a process that has been designated for debugging is generated. The control program request is placed into a memory buffer associated with the thread by the debugger. The memory buffer is passed to a control program. A plurality of memory buffers is monitored. Each memory buffer in the plurality of memory buffers is associated with a different thread of the process. At least one memory buffer in the plurality of memory buffers is determined to include debugging event information from the control program determining. The debugging event information is processed. The processing includes at least one of notifying a user of the debugging event information and generating at least one control program request for a thread associated with the at least one memory buffer.

Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.

Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.

Abstract: A method and information processing system facilitate debugging of a multi-threaded application. A control program request associated with at least one thread of a process that has been designated for debugging is generated. The control program request is placed into a memory buffer associated with the thread by the debugger. The memory buffer is passed to a control program. A plurality of memory buffers is monitored. Each memory buffer in the plurality of memory buffers is associated with a different thread of the process. At least one memory buffer in the plurality of memory buffers is determined to include debugging event information from the control program determining. The debugging event information is processed. The processing includes at least one of notifying a user of the debugging event information and generating at least one control program request for a thread associated with the at least one memory buffer.

Abstract: A method and information processing system facilitate debugging of a multi-threaded application. A control program request associated with at least one thread of a process that has been designated for debugging is generated. The control program request is placed into a memory buffer associated with the thread by the debugger. The memory buffer is passed to a control program. A plurality of memory buffers is monitored. Each memory buffer in the plurality of memory buffers is associated with a different thread of the process. At least one memory buffer in the plurality of memory buffers is determined to include debugging event information from the control program determining. The debugging event information is processed. The processing includes at least one of notifying a user of the debugging event information and generating at least one control program request for a thread associated with the at least one memory buffer.

Abstract: A processor-implemented method for designing, developing, implementing and maintaining a core service related to a database is provided. The processor-implemented method may include displaying a graphical user interface and identifying, from the graphical user interface, the core service. Then the processor-implemented method may include determining, from the graphical user interface, a type of folder request based on the identified core service and accessing a folder based on the determining of the type of folder request. The processor-implemented method may further include determining a lock order based on the accessed folder; and manipulating the accessed folder based on the determining of the lock order.

Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.

Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.

Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.

Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.

Abstract: A processor-implemented method for designing, developing, implementing and maintaining a core service related to a database is provided. The processor-implemented method may include displaying a graphical user interface and identifying, from the graphical user interface, the core service. Then the processor-implemented method may include determining, from the graphical user interface, a type of folder request based on the identified core service and accessing a folder based on the determining of the type of folder request. The processor-implemented method may further include determining a lock order based on the accessed folder; and manipulating the accessed folder based on the determining of the lock order.

Abstract: A common symbol table is generated, which includes symbols of a plurality of independent applications. The symbols included in the common symbol table are common symbols of the applications. The bulky information associated with the common symbols are stored in the common symbol table, and stubs used to locate the common symbols are stored in local tables of the applications.

Abstract: A method and information processing system facilitate debugging of a multi-threaded application. A control program request associated with at least one thread of a process that has been designated for debugging is generated. The control program request is placed into a memory buffer associated with the thread by the debugger. The memory buffer is passed to a control program. A plurality of memory buffers is monitored. Each memory buffer in the plurality of memory buffers is associated with a different thread of the process. At least one memory buffer in the plurality of memory buffers is determined to include debugging event information from the control program determining. The debugging event information is processed. The processing includes at least one of notifying a user of the debugging event information and generating at least one control program request for a thread associated with the at least one memory buffer.

Abstract: A method and information processing system facilitate debugging of a multi-threaded application. A control program request associated with at least one thread of a process that has been designated for debugging is generated. The control program request is placed into a memory buffer associated with the thread by the debugger. The memory buffer is passed to a control program. A plurality of memory buffers is monitored. Each memory buffer in the plurality of memory buffers is associated with a different thread of the process. At least one memory buffer in the plurality of memory buffers is determined to include debugging event information from the control program determining. The debugging event information is processed. The processing includes at least one of notifying a user of the debugging event information and generating at least one control program request for a thread associated with the at least one memory buffer.

Abstract: Managing shared data objects to share data between computer processes, including a method for executing a plurality of independent processes on an application server, the processes including a first process and a second process. A shared memory utilized by the plurality of independent processes is provided. A single copy of the data and metadata are stored in the shared memory. The metadata includes an address of the data. The first process initiates the storing of the data in the shared memory. An address of the metadata is transferred from the first process to the second process to notify the second process about the data. The second process determines the address of the shared memory by reading the metadata. The data in the shared memory is accessed by the second process.

Abstract: A system for sharing data between computer processes. The system includes a processor configured to implement a method that includes executing a plurality of independent processes on an application server, the processes including a first process and a second process. A shared memory utilized by the plurality of independent processes is provided. A single copy of the data and metadata are stored in the shared memory. The metadata includes an address of the data. The first process initiates the storing of the data in the shared memory. An address of the metadata is transferred from the first process to the second process to notify the second process about the data. The second process determines the address of the shared memory by reading the metadata. The data in the shared memory is accessed by the second process.

Abstract: A system for sharing data between computer processes. The system includes a processor configured to implement a method that includes executing a plurality of independent processes on an application server, the processes including a first process and a second process. A shared memory utilized by the plurality of independent processes is provided. A single copy of the data and metadata are stored in the shared memory. The metadata includes an address of the data. The first process initiates the storing of the data in the shared memory. An address of the metadata is transferred from the first process to the second process to notify the second process about the data. The second process determines the address of the shared memory by reading the metadata. The data in the shared memory is accessed by the second process.

Abstract: A method for enhancing debugger performance of hardware assisted breakpoints across multiple units includes deferring all active location breakpoints within the multiple modules, and subsequently activating each valid location breakpoint in a present one of the multiple modules being entered.