Abstract: A magnetic tunnel junction device is disclosed comprising a first device layer comprising a material having a magnetic moment; a second device layer comprising a material having a magnetic moment, e.g., wherein the magnetic moment of the material of the second device layer is different from that of the material of the first device layer; and a barrier layer, e.g., tunnel barrier, having a first interface to the first device layer comprising predominantly of a scandium nitride (ScN) material and having a second interface to the second device layer comprising predominantly of a scandium nitride (ScN) material.

Abstract: A method of dispersing fine particles in a spray including the steps of providing a liquid carrier having a critical point and fine particles of at least one material. The fine particles are dispersed in the liquid carrier. A supercritical carrier containing dispersed particles is created by driving the liquid carrier containing dispersed fine particles above the critical point. The pressure of the supercritical carrier containing dispersed particles is reduced thereby forming a vapor carrier containing dispersed particles therein. The vapor carrier containing dispersed fine particles is then discharged.

Abstract: A combustor includes a combustor head with an integrated counter-flow heat exchanger. The combustor head defines a combustion chamber and has a surface accessible for external delivery of thermal energy. The counter-flow heat exchanger has a fuel channel extending between a fuel inlet and a fuel outlet coupled to the combustion chamber, an exhaust channel extending between an exhaust inlet coupled to the combustion chamber and an exhaust outlet, and a shared wall between the fuel channel and the exhaust channel for transfer of thermal energy therebetween.

Abstract: High quality monocrystalline metal oxide layers are grown on a monocrystalline substrate such as a silicon wafer. The monocrystalline metal oxide is grown on the silicon substrate at a temperature low enough to prevent deleterious and simultaneous oxidation of the silicon substrate. After a layer of 1-3 monolayers of the monocrystalline oxide is grown, the growth is stopped and the crystal quality of that layer is improved by a higher temperature anneal. Following the anneal, the thickness of the layer can be increased by restarting the low temperature growth. An amorphous silicon oxide layer can be grown at the interface between the monocrystalline metal oxide layer and the silicon substrate after the thickness of the monocrystalline oxide reaches a few monolayers.

Abstract: A fuel cell device and method of forming the fuel cell device including a base portion having a major surface. At least one fuel cell membrane electrode assembly is formed on the major surface of the base portion. A water recovery and recirculation system is defined in a cap portion and in communication with a water recovery and recirculation channel defined in the base portion. The water recovery and recirculating system is formed to collect reaction water from the cathode side of the at least one fuel cell membrane electrode assembly for recirculation to the anode side of the fuel cell membrane electrode assembly. An exhaust separation chamber is defined in the base portion and communicating with the fuel cell membrane electrode assembly for the exhausting of generated gases.

Abstract: A thermoelectric material is disclosed that is manufactured from a method including the steps of: providing a Group IV element boride, and doping the Group IV element boride with a doping element chosen from one of the column III, IV, V elements, wherein the doping element is different from the Group IV element in the Group IV element boride, and the doping element is not boron. An alternate method of fabricating a thermoelectric material includes the steps of simultaneously growing on a substrate a Group IV element boride and at least one doping element chosen from one of the Group III, IV, or V elements wherein the doping element is different than the Group IV element in the Group IV element boride and the doping element is not boron.

Abstract: High quality monocrystalline metal oxide layers are grown on a monocrystalline substrate such as a silicon wafer. The monocrystalline metal oxide is grown on the silicon substrate at a temperature low enough to prevent deleterious and simultaneous oxidation of the silicon substrate. After a layer of 1-3 monolayers of the monocrystalline oxide is grown, the growth is stopped and the crystal quality of that layer is improved by a higher temperature anneal. Following the anneal, the thickness of the layer can be increased by restarting the low temperature growth. An amorphous silicon oxide layer can be grown at the interface between the monocrystalline metal oxide layer and the silicon substrate after the thickness of the monocrystalline oxide reaches a few monolayers.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. The compliant substrate includes an accommodating buffer layer comprising a layer of monocrystalline oxide having a niobium concentration that provides for substantial lattice matching of the accommodating buffer layer to the overlying monocrystalline material layer. The monocrystalline oxide of the accommodating buffer layer is selected to be lattice matched to the underlying monocrystalline substrate. The accommodating buffer layer may be spaced apart from the underlying monocrystalline substrate by an amorphous interface layer. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer.

Abstract: A thermoelectric material comprising a Group IV element boride doped with one of the Group III, IV, or V elements, wherein the doping element is different from the Group IV element in the Group IV element boride, and the doping element is not boron. A method of fabricating a thermoelectric material including the steps of: providing a Group IV element boride, and doping the Group IV element boride with a doping element chosen from one of the column III, IV, or V elements, wherein the doping element is different from the Group IV element in the Group IV element boride, and the doping element is not boron. An alternate method of fabricating a thermoelectric material is also disclosed including the steps of simultaneously growing on a substrate a Group IV element boride and at least one doping element chosen from one of the Group III, IV, or V elements wherein the doping element is different than the Group IV element in the Group IV element boride and the doping element is not boron.

Abstract: A fuel cell device and method of forming the fuel cell device including a base portion having a major surface. At least one fuel cell membrane electrode assembly is formed on the major surface of the base portion. A water recovery and recirculation system is defined in a cap portion and in communication with a water recovery and recirculation channel defined in the base portion. The water recovery and recirculating system is formed to collect reaction water from the cathode side of the at least one fuel cell membrane electrode assembly for recirculation to the anode side of the fuel cell membrane electrode assembly. An exhaust separation chamber is defined in the base portion and communicating with the fuel cell membrane electrode assembly for the exhausting of generated gases.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A thermo-electric device is integrated into the semiconductor structure.

Abstract: A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Abstract: A thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat including a condenser, a heat source, such as steam, and at least one thermoelectric module. The condenser includes a plurality of condenser tubes each having included therein a heat extractor. The heat source is in communication with the condenser and is characterized as providing thermal energy to the condenser. The at least one thermoelectric module, including a plurality of thermoelectric elements, is positioned in communication with at least one of the plurality of condenser tubes so that thermal energy flows through the thermoelectric elements thereby generating electrical power.

Abstract: A field effect transistor with an enhanced dielectric constant gate insulator including spaced apart source and drain terminals positioned on a substrate structure so as to define a gate area therebetween. A layer of laterally strained, enhanced dielectric constant dielectric material is epitaxially grown on the substrate structure in the gate area, and a gate metal is positioned on the layer of dielectric material to form a gate terminal in the gate area.

Abstract: A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Abstract: Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of nano-memory elements, nano-diodes coupling the address ports to a high dimensional plurality of the plurality of nano-memory elements, and data output ports and structure coupled to the plurality of nano-memory elements. The high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).

Abstract: A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.

Abstract: A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500.degree. C. to 750.degree. C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10.sup.-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi.sub.2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (13) of ferroelectric material disposed on a semiconductor substrate (11) and a gate electrode (17) formed on a portion (26) of the layer (13) of ferroelectric material. The portion (26) of the layer (13) of ferroelectric material sandwiched between a semiconductor substrate (11) and a gate electrode (17) retains its ferroelectric activity. The portions (21, 22) of the layer (13) of ferroelectric material adjacent the portion (26) are damaged and thereby rendered ferroelectrically inactive. A source contact (31) and a drain contact (32) are formed through the damaged portions (21, 22) of the layer (13) of ferroelectric material.