Patents by Inventor Daniel Sarlette

Daniel Sarlette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837280
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 5, 2017
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Publication number: 20160343577
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Patent number: 9437440
    Abstract: A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Publication number: 20140141602
    Abstract: A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.
    Type: Application
    Filed: October 25, 2013
    Publication date: May 22, 2014
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Patent number: 6645683
    Abstract: In the control method for photolithographic processes, line width errors and/or positional errors measured on processed semiconductor wafers are used to calculate correction values for the exposure intensity and/or the xy positioning of the semiconductor wafer. Optimized correction values for a subsequent batch of semiconductor wafers to be processed are calculated by averaging correction values over a number of previously calculated correction values. Only those correction values which lie within a predetermined value range are used in the average.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: November 11, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Luhn, Daniel Sarlette
  • Publication number: 20020012861
    Abstract: In the control method for photolithographic processes, line width errors and/or positional errors measured on processed semiconductor wafers are used to calculate correction values for the exposure intensity and/or the xy positioning of the semiconductor wafer. Optimized correction values for a subsequent batch of semiconductor wafers to be processed are calculated by averaging correction values over a number of previously calculated correction values. Only those correction values which lie within a predetermined value range are used in the average.
    Type: Application
    Filed: July 31, 2001
    Publication date: January 31, 2002
    Inventors: Gerhard Luhn, Daniel Sarlette