Abstract: A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including address, data, opcodes, and various flags registers that are used by other subsystems including the program buffer, burst read module, register block, and microcontroller. In addition, the command decoder contains clock synchronization logic, controls the sleep function of the microcontroller and serves as a test mode controller.

Abstract: A system and method for expanding the command set of a memory controller is provided. In one implementation, the method includes decoding a first plurality of commands through a command decoding state machine, and in response to the command decoding state machine decoding an extended command, waking the microcontroller to process an additional command other than a command among the first plurality of commands. The extended command is a command that notifies the microcontroller of the additional command to be processed.

Abstract: Some embodiments includes a digital control system having a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control, and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug. Other embodiments are described.

Abstract: The present invention provides method and apparatus for synchronizing data between different clock domains in a memory controller. In one embodiment, a memory controller is provided that includes a command decoder and synchronizing logic. The command decoder is operable to receive a command in accordance with a first clock domain. The synchronizing logic synchronizes the command to a second clock domain that is different from the first clock domain, and includes a first synchronization flop and a second synchronization flop operable to prevent metastability associated with synchronizing the command to the second clock domain.

Abstract: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.

Abstract: A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including address, data, opcodes, and various flags registers that are used by other subsystems including the program buffer, burst read module, register block, and microcontroller. In addition, the command decoder contains clock synchronization logic, controls the sleep function of the microcontroller and serves as a test mode controller.

Abstract: A system, computer program product, and method for controlling access to a system memory space are provided. The system includes a processor operable to perform an operation on the memory space and a bus monitor operable to monitor the processor. The bus monitor includes a definition for specifying the operation as either permissible or impermissible for a region of the memory space. The bus monitor is further operable to block the processor from performing the operation in response to the definition specifying the operation as impermissible.

Abstract: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.