Patents by Inventor Daniel Selle

Daniel Selle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120324776
    Abstract: The invention comprises a ring alignment bar, a mount extension rod, a bore rod, a lower connector block, a vertical connector rod, an upper connector block, and a bore extension rod. The ring alignment bar is installed in the rings of a telescopic sight mount on a firearm to bring the rings into concentric alignment with each other. The mount extension rod indicates lateral alignment between the rings and barrel of the firearm. The bore rod fits into the muzzle of the firearm. The upper and lower connector blocks, vertical connector rod, and bore extension rod fit together to indicate alignment in a vertical plane between the rings and the bore of the firearm.
    Type: Application
    Filed: December 27, 2011
    Publication date: December 27, 2012
    Inventor: Daniel Selle Hepler
  • Patent number: 5124275
    Abstract: A method of manufacturing by autoalignment an integrated semiconductor device is set forth comprising the realization on respective semiconductor layers of a first encapsulated electrode contact E provided with spacers and of a second autoaligned electrode contact B on the first contact thus equipped, which process comprises at least: a.sub.0) the formation of a first and a second semiconductor layer for receiving the first and the second electrode contact, respectively; b.sub.0) the formation by a so-called image reversal method of an opening B.sub.o with overhanging sides in a photoresist layer deposited on the first semiconductor layer; c.sub.0) the deposition of a first metal layer forming the first electrode contact E in this opening, which contact has sides F.sub.2 of a lower height than those F.sub.1 of the photoresist layer, these sides F.sub.2 having upper edges which are situated laterally at a small distance from the overhanging sides F.sub.
    Type: Grant
    Filed: February 5, 1991
    Date of Patent: June 23, 1992
    Assignee: U.S. Philips Corporation
    Inventors: Daniel Selle, Dominique Carisetti
  • Patent number: 4889821
    Abstract: A method of manufacturing a hetero-junction bipolar transistor especially of gallium arsenide comprising the formation of epitaxial layers superimposed to obtain a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base region (31, 30) or of the n.sup.+ type to form collector contact islands (20). This method also including the formation of base contacts B (70) having the dimensions B.sub.0 and located at a relative distance of E.sub.1, then covering the metallization (70) of pads (81) of silica (Si.sub.3 N.sub.4) having edges perpendicular to the plane of the layers on which bear spacers of silicon nitride (Si.sub.3 N.sub.4) (52) having dimensions h.sub.1 defining with a high precision the dimension E.sub.0 =B.sub.1 -2h of the emitter contact E and the distances between the different collector (90), base (70) and emitter (90) contacts C, B and E, respectively.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: December 26, 1989
    Assignee: U.S. Philips Corp.
    Inventors: Daniel Selle, Philippe Boissenot
  • Patent number: 4889824
    Abstract: A method of manufacturing a hetero-junction bipolar transistor, especially of gallium arsenide, comprising the step of forming superimposed epitaxial layers for forming a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base regions (31,30) or of the n.sup.+ type to obtain collector contact islands (20). This method also includes the formation by a controlled etching into a germanium layer (50) formed at the surface of these layers, of pads having a profile such that their tips define with a very high precision openings (E.sub.1), of which the distance (E.sub.0) between the edges defines the emitter contact region, while their edges have a concavity turned towards the exterior of the device.Application integrated circuits on gallium arsenide.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: December 26, 1989
    Assignee: U.S. Philips Corp.
    Inventors: Daniel Selle, Philippe Boissenot, Patrick Rabinzohn