Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.

Abstract: The present invention is a means for forming interconnect or other circuitry on a surface. The present invention utilizes a topology into which one or more layers of materials are deposited, the top layer of which is typically an etch resistant (or slow etching) material. These materials are then planarized and further processed, typically by etching. The present invention enables more conductive circuitry on the surface than would be possible with a damascene process because the present invention does not rely upon planarization to define the circuit features. Instead, the present invention uses planarization to define a pattern in a masking material that shields material beneath that masking material during subsequent processing. As a result, the material remaining after processing can extend above the topology thereby providing a greater cross section to the features and a correspondingly greater conductivity.