Abstract: A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands.

Abstract: A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands.

Abstract: A hardware accelerator computes a scalar dot product given by ?i=0N?1diPi where di is a scalar of length b bits and Pi is an element in a group. The hardware accelerator includes a plurality A of accumulators addressed by corresponding contiguous partitions of the scalar di, each partition being of length c such that A = ? b c ? and each accumulator containing a plurality B of buckets where B=2c. The value of Pi is entered into each empty accumulator bucket whose value corresponds to the weight of the respective partition associated with the corresponding accumulator or is added to a non-zero value that is already in the bucket, the sum replacing the previous value. An accumulator sums the values in the respective buckets of each accumulator so as to derive A sums, and sums the A computed sums to derive the scalar dot product.

Abstract: In some aspects, the disclosure is directed to methods and systems for topology configuration of an array of packet processing elements via a topology configuration packet. Each processing element may include input packet busses from a first plurality of neighboring processing elements and output packet busses to a second plurality of neighboring processing elements. Each processing element may receive the configuration packet from one of the first plurality of neighboring elements, set its own topology configuration register according to predetermined values within the packet, and forward the packet out all of its outputs, in the same manner as a standard packet.

Abstract: In some aspects, the disclosure is directed to methods and systems for topology configuration of an array of packet processing elements via a topology configuration packet. Each processing element may include input packet busses from a first plurality of neighboring processing elements and output packet busses to a second plurality of neighboring processing elements. Each processing element may receive the configuration packet from one of the first plurality of neighboring elements, set its own topology configuration register according to predetermined values within the packet, and forward the packet out all of its outputs, in the same manner as a standard packet.