Patents by Inventor Daniel Skinner

Daniel Skinner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230072539
    Abstract: Introduced here is an artificial intelligence system designed for machine learning. The system may be based on a neuromorphic computational model that learns spatial patterns in inputs using data structures called Sparse Distributed Representations (SDRs) to represent the inputs. Moreover, the system can generate signatures for these SDRs, and these signatures may be used to create definitions of classes or subclasses for classification purposes.
    Type: Application
    Filed: July 29, 2022
    Publication date: March 9, 2023
    Inventors: Harold B Noyes, David Roberts, Russell B. Lloyd, William Tiffany, Jeffery Tanner, Terrence Leslie, Daniel Skinner, Indranil Roy
  • Publication number: 20220273215
    Abstract: A pressure monitor is provided for reporting pressure exerted by each of a plurality of core muscles of a user, the pressure monitor comprising: an adjustable belt, the adjustable belt including an inner surface and an outer surface; a plurality of pressure sensors movably mounted on the inner surface of the adjustable belt; a microcontroller which is mounted on the belt and is in electronic communication with each of the plurality of pressure sensors; and a user interface, the user interface in communication with the microcontroller.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 1, 2022
    Inventor: Daniel SKINNER
  • Publication number: 20220164637
    Abstract: Introduced here are integrated circuits (also referred to as “chips”) that can be implemented in a neural processing unit. At a high level, the goal of these chips is to provide higher performance for machine learning algorithms than conventional processing units would. To accomplish this, the neural processing unit can include multiple computing components, each of which is able to independently determine the overlap between encoded data provided as input and values stored in a memory.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 26, 2022
    Inventors: Harold B. Noyes, David Roberts, Russell Lloyd, William Tiffany, Jeffery Tanner, Terrence Leslie, Daniel Skinner, Indranil Roy
  • Patent number: 10796746
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
  • Publication number: 20190027208
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
  • Patent number: 10115449
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 30, 2018
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
  • Patent number: 9915013
    Abstract: A shed forming device for a weaving machine comprising motion systems consisting of hooks that are moveable up and down, transmission elements to transmit the hook motion to a carrier for warp threads, a first force element to exert a downward-directed force on the carrier, and an energy buffer and a second force element to exert a force on an element of the motion system that results in an upward-directed force on the carrier so that the element is so deformed or displaced that the elements of the motion system are kept under tension.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 13, 2018
    Assignee: NV MICHEL VAN DE WIELE
    Inventors: Bram Vanderjeugt, Matthew Theobald, Daniel Skinner
  • Publication number: 20170167059
    Abstract: A shed forming device for a weaving machine comprising motion systems consisting of hooks that are moveable up and down, transmission elements to transmit the hook motion to a carrier for warp threads, a first force element to exert a downward-directed force on the carrier, and an energy buffer and a second force element to exert a force on an element of the motion system that results in an upward-directed force on the carrier so that the element is so deformed or displaced that the elements of the motion system are kept under tension.
    Type: Application
    Filed: July 20, 2015
    Publication date: June 15, 2017
    Inventors: Bram VANDERJEUGT, Matthew THEOBALD, Daniel SKINNER
  • Publication number: 20170133080
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: DEAN GANS, MOO SUNG CHAE, DANIEL SKINNER
  • Patent number: 9601182
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner
  • Publication number: 20160329090
    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 10, 2016
    Inventors: Dean Gans, Moo Sung Chae, Daniel Skinner