Abstract: An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.

Abstract: An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.

Abstract: Structure and method for a backside capacitor using through-substrate vias (TSVs) and backside metal plates. The structure includes: a substrate, a device layer over the substrate, a first plurality of metal layers connected to the device layer, where the device layer and the first plurality of metal layers are disposed on a first side of the substrate, and a second plurality of metal layers disposed on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor and where a plurality of through-substrate vias (TSVs) extend between the first plurality of metal layers and the second plurality of metal layers.

Abstract: Structure and method for a backside capacitor using through-substrate vias (TSVs) and backside metal plates. The structure includes: a substrate, a device layer over the substrate, a first plurality of metal layers connected to the device layer, where the device layer and the first plurality of metal layers are disposed on a first side of the substrate, and a second plurality of metal layers disposed on a second side of the substrate opposite the first side, where the second plurality of metal layers form at least one capacitor and where a plurality of through-substrate vias (TSVs) extend between the first plurality of metal layers and the second plurality of metal layers.

Abstract: An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

Abstract: An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.

Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

Abstract: An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.

Abstract: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.

Abstract: A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The exemplary method also includes generating statistics for the set of components. The statistics are related to clock gating testing to identify whether one or more components of the set of components can be clock gated.

Abstract: Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

Abstract: Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent case. The method also includes eliminating the feedback loop if function F depends only on Q with a positive polarity or leaving the feedback loop if function F depends on Q in both positive and negative polarities.

Abstract: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power tables are created based upon the macro's input switching factor percentage and the clock activation percentage. These power tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate energy tables are produced.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro containing internal clock gating. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain internal clock gating and multiple clock gating inputs. To achieve accurate power estimates a voltage supply is connected to each clock activate signal. Energy tables are then created based upon the macro's input switching factor percentage and clock activation percentage. These power tables are generated from a minimum number of power simulations. By incorporating internally generated clock activate signals into the power estimations the macro energy tables are much more accurate.

Abstract: An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.