Patents by Inventor Daniel Staver

Daniel Staver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5111421
    Abstract: A versatile floating point adder which performs high speed floating point addition or subtraction on operands supplied in a signed magnitude format includes separate exponent and mantissa data paths for processing the exponent fields and mantissa fields of the floating point binary numbers to be added or subtracted. The exponent data path computes the absolute difference between the exponents of the floating point numbers, passes the large exponent, and adjusts the large exponent by an amount needed to normalize the mantissa and to reflect an overflow in the mantissa addition/substration and mantissa rounding operations. The mantissa data path denormalizes one of the input mantissas, adds the two mantissas after the denormalization operation, post-normalizes the resulting mantissa, and rounds the mantissa to the correct precision.
    Type: Grant
    Filed: February 26, 1990
    Date of Patent: May 5, 1992
    Assignee: General Electric Company
    Inventors: Karl J. Molnar, Ho Chung-Yih, Daniel A. Staver, Barbara D. Molnar
  • Patent number: 5021987
    Abstract: Digital electronic apparatus for performing chain-serial matrix multiplications using a single pipeline multiplier supplies elements of the multiplicand and multiplier matrices to the digital memory from first and second memories. Each product matrix is temporarily stored in a third memory until such time as it is used to write the first memory for the next matrix multiplication in the series. This procedure avoids overwriting the first memory when its data are still required for application to the pipeline multiplier.
    Type: Grant
    Filed: August 31, 1989
    Date of Patent: June 4, 1991
    Assignee: General Electric Company
    Inventors: David S. K. Chan, Daniel A. Staver
  • Patent number: 5001647
    Abstract: An inertial transformation matrix generator generates a succession of Euler transformation matrices in inertial coordinates, and is useful for converting to inertial coordinates the responses of a sensor hard mounted on the hull of a craft (e.g., an aircraft). First, second and third rate-sensing gyros located proximately to said sensor are strapped down to the craft hull, and are oriented to sense the motion of the craft hull in three mutually orthogonal directions, for providing respective output signals indicative of components of craft hull motion in each of those three mutually orthogonal directions. The output signals of the gyros are digitized, and based on these digital signals successive incremental Euler transformation matrices are generated.
    Type: Grant
    Filed: August 31, 1989
    Date of Patent: March 19, 1991
    Assignee: General Electric Company
    Inventors: Stephen J. Rapiejko, David S. Chan, Daniel A. Staver, Nancy M. Clark
  • Patent number: 4901263
    Abstract: A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.
    Type: Grant
    Filed: September 12, 1988
    Date of Patent: February 13, 1990
    Assignee: General Electric Company
    Inventors: Chung-Yih Ho, Karl J. Molnar, Daniel A. Staver
  • Patent number: 4841467
    Abstract: A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.
    Type: Grant
    Filed: October 5, 1987
    Date of Patent: June 20, 1989
    Assignee: General Electric Company
    Inventors: Chung-Yih Ho, Karl J. Molnar, Daniel A. Staver