Abstract: A voltage transient protection circuit is provided for protecting a memory device such as a solid state memory cartridge from an undesired control signal which may occur during voltage transients in the primary supply voltage for such memory device. A transient detector detects transients occurring in the primary supply voltage. An isolation circuit is provided in the control bus, such isolation circuit being activated when a transient in the primary supply voltage is detected. A secondary voltage source supplies voltage to the transient detector and the isolation circuit sufficiently long while the primary voltage is fluctuating during a transient to permit the isolation circuit to isolate the control signal(s)el from said memory device.