Abstract: A method is described by which an electrical path is created between layers on a printed circuit board (PCB) without the use of plated through holes (PTH). Through the use of a liquid solder or conductive epoxy injection fixture, a conductive path is created in pre-drilled holes forming an electrical connection between internal PCB metal layers and surface mounted components without the creation of parasitic stubs on the signal nets.

Abstract: A method is described by which an electrical path is created between layers on a printed circuit board (PCB) without the use of plated through holes (PTH). Through the use of a liquid solder or conductive epoxy injection fixture, a conductive path is created in pre-drilled holes forming an electrical connection between internal PCB metal layers and surface mounted components without the creation of parasitic stubs on the signal nets.

Abstract: Wiring structures and methods for integrated circuit designs which are adapted to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle time overlap violations in launch/capture clocking systems are provided, whereby the A/B/C (test/launch/capture) clock wire nets are designed using a five parallel track wire segment, in which the B clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, the C clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, and where the A test clock wire is represented as a single track comprising test signal wire disposed between the B and C signal wires.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: A system, method and storage medium for providing redundant I/O access between a plurality of interconnected processor nodes and I/O resources. The method includes determining whether a primary path between the interconnected processor nodes and the I/O resources is operational, where the primary path includes a first processor node and a primary multiplexer. If the primary path is operational, the transactions are routed via the primary path. If the primary path is not operational, the transactions are routed between the interconnected processor nodes and the I/O resources via an alternate path that includes a second processor node and an alternate multiplexer.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: An optoelectronic assembly for an electronic system includes a support electronic chip set configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions. A first substrate having a first surface and an opposite second surface is in communication with the support electronic chip set via the first surface while a second substrate is in communication with the second surface of the first substrate. The second substrate is configured for mounting at least one of data processing, data switching and data storage chips. An optoelectronic transducer is in signal communication with the support electronic chip set and an optical fiber array is aligned at a first end with the optoelectronic transducer and with an optical signaling medium at a second end.

Abstract: An optoelectronic assembly for a computer system includes an electronic chip(s), a substrate, an electrical signaling medium, an optoelectronic transducer, and an optical coupling guide. The electronic chip(s) is in communication with the substrate, which is in communication with a first end of the electrical signaling medium. A second end of the electrical signaling medium is in communication with the optoelectronic transducer, and includes the optical coupling guide for aligning an optical signaling medium with the optoelectronic transducer. An electrical signal from the electronic chip is communicated to the optoelectronic transducer via the substrate and the electrical signaling medium. The optical transducer and electronic chip(s) share a common heat spreader, and communication to other groups of electronic chip(s) is done without the need for communication via a second level electrical package.

Abstract: A clock signal distribution system for a digital electronic system operating at high clock speed and short cycle times distributes a primary clock signal which is of relatively low frequency through conventional hardware. A high frequency secondary clock signal is generated using a phase locked loop to maintain high accuracy synchronization with the primary clock. Delay means are provided for both the primary and secondary clock signals to provide compensation of propagation time or to provide desired offsets. The phase locked loop arrangements with delays can be cascaded to provide flexibility of both frequency and phase of signals throughout the system, any or all of which may be maintained in synchronism with the primary clock. A dynamic digital transfer function generator is also used within the phase locked loop to achieve particular synchronization functions.