Patents by Inventor Daniel Sykora

Daniel Sykora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130335426
    Abstract: Techniques are presented for controlling the amount of temporal noise in certain animation sequences. Sketchy animation sequences are received in an input in a digital form and used to create an altered version of the same animation with temporal coherence enforced down to the stroke level, resulting in a reduction of the perceived noise. The amount of reduction is variable and can be controlled via a single parameter to achieve a desired artistic effect.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: DISNEY ENTERPRISES, INC.
    Inventors: Gioacchino NORIS, Daniel SYKORA, Stelian COROS, Alexander HORNUNG, Brian WHITED, Maryann SIMMONS, Markus GROSS, Robert SUMNER
  • Publication number: 20130241934
    Abstract: A method is provided for sketch segmentation via smart scribbles, the results of which are especially suitable for interactive real-time graphics editing applications. A vector-based drawing may be segmented into labels based on input scribbles provided by a user. By organizing the labeling as an energy minimization problem, an approximate solution can be found using a sequence of binary graph cuts for an equivalent graph, providing an optimized implementation in a polynomial time suitable for real-time drawing applications. The energy function may include time, proximity, direction, and curvature between strokes as smoothness terms, and proximity, direction, and oriented curvature between strokes and scribbles as data terms. Additionally, the energy function may be modified to provide for user control over locality control, allowing the selection of appropriately sized labeling regions by scribble input speed or scribble input pressure.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Applicant: DISNEY ENTERPRISES, INC.
    Inventors: Gioacchino Norris, Daniel Sykora, Ariel Shamir, Stelian Coros, Alexander Hornung, Robert Sumner, Maryann Simmons, Brian Whited, Markus Gross
  • Patent number: 8533139
    Abstract: Approaches for optimizing computation of minimum cut or maximum flow on graphs comprising a plurality of nodes and edges with grid-like topologies are disclosed. Embodiments exploit the regular structure of input graphs to reduce the memory bandwidth—a main bottleneck of popular max-flow/min-cut algorithms based on finding augmenting paths on a residual graph (such as Ford-Fulkerson [1956] or Boykov-Kolmogorov [2004]). Disclosed embodiments allow more than 200% speed-up without sacrificing optimality of the final solution, which is crucial for many computer vision and graphics applications. Method and system embodiments replace standard linked list representation of general graphs with a set of compact data structures with blocked memory layout that enables fixed ordering of edges and implicit branchless addressing of nodes.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: September 10, 2013
    Assignee: Czech Technical University in Prague, Faculty of Electrical Engineering
    Inventors: Ond{hacek over (r)}ej Jamri{hacek over (s)}ka, Daniel Sýkora
  • Publication number: 20130060724
    Abstract: Approaches for optimizing computation of minimum cut or maximum flow on graphs comprising a plurality of nodes and edges with grid-like topologies are disclosed. Embodiments exploit the regular structure of input graphs to reduce the memory bandwidth—a main bottleneck of popular max-flow/min-cut algorithms based on finding augmenting paths on a residual graph (such as Ford-Fulkerson [1956] or Boykov-Kolmogorov [2004]). Disclosed embodiments allow more than 200% speed-up without sacrificing optimality of the final solution, which is crucial for many computer vision and graphics applications. Method and system embodiments replace standard linked list representation of general graphs with a set of compact data structures with blocked memory layout that enables fixed ordering of edges and implicit branchless addressing of nodes.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: Czech Technical University in Prague, Faculity of Electrical Engineering
    Inventors: Ondrej Jamriska, Daniel Sýkora