Abstract: Anti-blooming control in overflow image sensor pixel. At least one example is an image sensor pixel comprising: a photodetector positioned in a semiconductor substrate; a gate oxide layer positioned on the semiconductor substrate; a floating diffusion; a transfer gate positioned on the gate oxide layer; a first anti-blooming implant positioned in the semiconductor substrate, wherein the first anti-blooming implant is coupled to the photodetector and the floating diffusion; and a second anti-blooming implant positioned in the semiconductor substrate, wherein the second anti-blooming implant is coupled to the photodetector and a voltage source contact.

Abstract: An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. A buried channel may be formed under the transfer gate. The buried channel may extend from the floating diffusion to overlap a portion of the transfer gate without extending completely beneath the transfer gate or reaching the photodiode. The buried channel may provide a path for antiblooming current from the photodiode to reach the floating diffusion, while allowing for the transfer gate off voltage to remain high enough to prevent transfer gate dark current from flowing into the photodiode.

Abstract: An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. A buried channel may be formed under the transfer gate. The buried channel may extend from the floating diffusion to overlap a portion of the transfer gate without extending completely beneath the transfer gate or reaching the photodiode. The buried channel may provide a path for antiblooming current from the photodiode to reach the floating diffusion, while allowing for the transfer gate off voltage to remain high enough to prevent transfer gate dark current from flowing into the photodiode.

Abstract: An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500° C. and 550° C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.

Abstract: An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500° C. and 550° C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.

Abstract: An image sensor may include isolation regions that are formed in between photodiodes. These isolation regions may prevent cross-talk and improve the performance of the image sensor. The isolation regions may include a conductive layer that is electrically connected to a bias voltage supply line. Biasing the conductive layer may result in a charge inversion in the substrate adjacent to the conductive layer. The charge inversion may prevent the generation of dark current. The conductive layer may be formed on a liner oxide layer in trenches formed in epitaxial silicon. A connecting layer may be used to electrically connect each conductive layer. The connecting layer may be formed integrally with the conductive layer or formed from a separate material.

Abstract: An image sensor may include isolation regions that are formed in between photodiodes. These isolation regions may prevent cross-talk and improve the performance of the image sensor. The isolation regions may include a conductive layer that is electrically connected to a bias voltage supply line. Biasing the conductive layer may result in a charge inversion in the substrate adjacent to the conductive layer. The charge inversion may prevent the generation of dark current. The conductive layer may be formed on a liner oxide layer in trenches formed in epitaxial silicon. A connecting layer may be used to electrically connect each conductive layer. The connecting layer may be formed integrally with the conductive layer or formed from a separate material.

Abstract: An image sensor may include isolation regions that are formed in between photodiodes. These isolation regions may prevent cross-talk and improve the performance of the image sensor. The isolation regions may be made of epitaxial silicon. The epitaxial silicon may be grown in trenches formed in a substrate using an etching process. Portions of the substrate may be protected from the etching process with a hard mask layer. Photodiodes may later be implanted in these protected portions of the substrate after the isolation regions have been formed. The epitaxial silicon may be boron-doped or antimony-doped epitaxial silicon with a concentration of boron or antimony between 1016 cm3 and 1018 cm3.

Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.

Abstract: A nanotubular MOSFET device extends a scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.

Abstract: A nanotubular MOSFET device extends a scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.