Patents by Inventor Daniel Thanh Khae Pham

Daniel Thanh Khae Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits having gate cap protection and methods of forming the same
    Patent number: 9269611
    Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: February 23, 2016
    Assignees: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Thanh Khae Pham, Xiuyu Cai, Bala Subramanian Pranatharthi Haran, Charan Veera Venkata Satya Surisetty, Jin Wook Lee, Shom Ponoth, David V. Horak
  • INTEGRATED CIRCUITS HAVING GATE CAP PROTECTION AND METHODS OF FORMING THE SAME
    Publication number: 20150206844
    Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 23, 2015
    Applicants: International Business Machines Corporation, Globalfoundries, Inc.
    Inventors: Daniel Thanh Khae Pham, Xiuyu Cai, Bala Subramanian Pranatharthi Haran, Charan Veera Venkata Satya Surisetty, Jin Wook Lee, Shom Ponoth, David V. Horak