Abstract: One exemplary embodiment describes an integrated circuit, comprising a multiplicity of scan flip-flops, a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises a chain of logic gates comprising a plurality of logic gates connected in succession, an input multiplexer for the chain, and a feedback line from an output connection of the last logic gate of the chain to a data input connection of the input multiplexer. Each ring oscillator circuit is assigned a scan flip-flop group that contains at least one of the multiplicity of scan flip-flops.

Abstract: An integrated circuit includes a ring oscillator circuit and a plurality of logic paths. Each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path. Each logic path, beginning with a first logic path, is assigned a respective subsequent logic path by virtue of the path output connection of the logic path being connected to a data input connection of the input multiplexer of the subsequent logic path. A last logic path of the logic paths is assigned the first logic path as subsequent logic path. For each logic path, the multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, it connects the data input connection of the input multiplexer to the path input connection of the logic path.

Abstract: An integrated circuit with self-test circuit is provided.

Abstract: One exemplary embodiment describes an integrated circuit, comprising a multiplicity of scan flip-flops, a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises a chain of logic gates comprising a plurality of logic gates connected in succession, an input multiplexer for the chain, and a feedback line from an output connection of the last logic gate of the chain to a data input connection of the input multiplexer. Each ring oscillator circuit is assigned a scan flip-flop group that contains at least one of the multiplicity of scan flip-flops.

Abstract: An integrated circuit with self-test circuit is provided.

Abstract: In accordance with one embodiment, a chip is provided which includes an interface configured to receive test data and masking data, a processing component having a plurality of scan chains. Each scan chain is configured to generate a test response on the basis of a processing of the test data. The chip further includes a compression circuit configured to compress the test responses generated by the scan chains to form a compressed test response, and a signature generating circuit configured to generate a signature on the basis of the compressed test response, depending on whether the masking data specify that the compressed test response is to be masked.