Abstract: An electronic circuit for cryptographic processing, comprising a first combinatorial logical circuit, arranged to perform a first set of logical operations on input data and to produce output data, the output data having a functional relation to the input data, further comprising at least a second combinatorial logical circuit, arranged to perform a second set of logical operations on the same input data and to produce output data, the output data having an identical functional relation to the input data, wherein the first set of logical operations is different from the second set of logical operations, and wherein the electronic circuit is arranged to dynamically select one combinatorial logical circuit, of a set comprising at least the first combinatorial logical circuit and the second combinatorial logical circuit, for performing logical operations on the input data and producing output data.

Abstract: An electronic device is provided which comprises a plurality of processing units (IP1-IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IP1-IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word-asynchronous communication.

Abstract: An electronic circuit is provided that comprises a plurality of storage elements (101-105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.

Abstract: Data is communicated between an asynchronously operating circuit (10) and a clocked operating sub-circuit (16, 17). A data signal is supplied from the asynchronously operating sub-circuit (10) accompanied by a blocking/non blocking control signal. A request signal from the asynchronously operating sub-circuit (10) when the data signal and the control signal are being supplied. The data is stored in response to the request at least if the control signal supplied with the data has a first value. The request signal is routed through a path through handshake elements in a handshake circuit (20, 30,40) that is arranged to generate an acknowledge signal in response to the request signal to the asynchronously operating sub-circuit (10).

Abstract: An electronic circuit for cryptographic processing, comprising a first combinatorial logical circuit, arranged to perform a first set of logical operations on input data and to produce output data, the output data having a functional relation to the input data, further comprising at least a second combinatorial logical circuit, arranged to perform a second set of logical operations on the same input data and to produce output data, the output data having an identical functional relation to the input data, wherein the first set of logical operations is different from the second set of logical operations, and wherein the electronic circuit is arranged to dynamically select one combinatorial logical circuit, of a set comprising at least the first combinatorial logical circuit and the second combinatorial logical circuit, for performing logical operations on the input data and producing output data.

Abstract: An asynchronously operated FIFO pipe-line (10a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a value of the data item. The FIFO pipelines (10a-d) comprise successive pipe-line stages, each pipe-line stage with respective handshake stages (12, 16) of each of the plurality of hand-shake chains. A coordination circuit (15) prevents handshakes in mutually different ones of handshake chains from overtaking one another. Preferably four phase handshake protocols are used with logic gates (26, 28) between the request line ((REQ1- i, REQ0- i) and the acknowledge line (ACK1- i, ACK0- i) at the input of a stage and a set-reset latch (20, 22) with a set input coupled to the output of the logic gate (26, 28).

Abstract: An electronic circuit is provided that comprises a plurality of storage elements (101-105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.

Abstract: FIG. 1c shows a logic tree 10c comprising a plurality of logic paths (27, 29, 31, 33) connected at a root 11c. The length of each path represents the delay of the path at a nominal supply voltage. The voltage supply structure for the logic tree 10c is partitioned as shown in FIG. 3c, according to the delay of each logic path. For example, logic path (29) having the worst-case delay is supplied a voltage level V1, for example the nominal supply voltage. Logic paths (27) and (31), having a shorter delay, are supplied a second voltage level V2, which is lower than the first voltage level V1. Logic path (33), having an even shorter delay, is supplied a third voltage level V3, which is lower than V2 and V1. The voltage structure enables the voltage level and hence power consumption to be reduced without increasing the overall worst-case delay of the logic tree 10c.