Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.

Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?yi)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Abstract: An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values of the same significance, a carry digit propagating signal and diagonal generation signals. The adder further including: an estimating circuit performing a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complement of the corresponding bit of significance of the first number; a second computing circuit, elaborating a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block applying to each estimated value of bit of significance k of the sum, k+1 corrections using the correcting signals, and delivering n bits of the sum.

Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.

Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?y1)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following Yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero Yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Abstract: An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series, each estimating block being capable of estimating each bit of the sum, and a correction circuit capable of generating a correction signal so as to correct each estimated bit of the sum after each estimate. Each correction signal of an estimated bit rank i of the sum is generated using the last rank i?1 estimated and corrected bit of the sum, the correction signal of said last rank i?1 bit, and the last estimated and corrected rank i?2 bit of the sum.

Abstract: An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values of the same significance, a carry digit propagating signal and diagonal generation signals. The adder further including: an estimating circuit performing a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complement of the corresponding bit of significance of the first number; a second computing circuit, elaborating a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block applying to each estimated value of bit of significance k of the sum, k+1 corrections using the correcting signals, and delivering n bits of the sum.