Abstract: Systems, methods, and apparatuses relating to interleaving data values. An embodiment includes decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and execution circuitry to execute the decoded instruction according to the opcode.

Abstract: Systems, methods, and apparatuses relating to a sign modification field for fused operations in a configurable spatial accelerator are described.

Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.

Abstract: Systems, methods, and apparatuses relating to interleaving data values. An embodiment includes decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and execution circuitry to execute the decoded instruction according to the opcode.

Abstract: An apparatus and method for complex matrix multiplication. For example, one embodiment of a processor comprises: a decoder to decode a first complex matrix multiplication instruction; execution circuitry to execute the first complex matrix multiplication instruction, the execution circuitry comprising parallel multiplication circuitry to multiply real values from the first plurality of real and imaginary values with corresponding real values from the second plurality of real and imaginary values to generate a first plurality of real products, to multiply imaginary values from the first plurality of real and imaginary values with corresponding imaginary values from the second plurality of real and imaginary values to generate a second plurality of real products; and addition/subtraction circuitry to subtract each real product in the second plurality of real products from a corresponding real product in the first plurality of real products to produce a corresponding real value in the result matrix.

Abstract: An apparatus and method for complex matrix conjugation and multiplication.

Abstract: An apparatus and method for complex matrix conjugation.

Abstract: An apparatus and method for complex matrix transpose and multiply.

Abstract: Systems, methods, and apparatuses relating to fused operations in a configurable spatial accelerator are described.

Abstract: A stabilizer assembly using a shoulder ring. The drilling tool may include a housing having one or more external splines disposed along an outer surface of the housing. The drilling tool may also include a rotatable shaft disposed inside the housing, the shaft having a downhole end portion configured to be coupled to a drill bit. The drilling tool may further include a stabilizer assembly movably coupled to the housing. In addition, the drilling tool may include a shoulder ring having one or more internal splines disposed on an inner surface thereof, the shoulder ring disposed around the housing and configured to prevent uphole movement of the stabilizer assembly when the one or more internal splines of the shoulder ring are engaged with the one or more external splines.

Abstract: A turbodrill using a balance drum. The turbodrill may include a housing having an upper end that is configured to be coupled to a drill string. The turbodrill may also include a rotatable shaft having a lower end configured to be coupled to a drill bit. The turbodrill may further include a balance drum assembly coupled to the shaft within the housing. In addition, the turbodrill may include a compliant mounting disposed between the balance drum assembly and the housing, where the compliant mounting is configured to allow displacement of the balance drum assembly within the housing.

Abstract: In a multicore programming environment comprising a plurality of processors in a plurality of categories, and having predetermined communication resources of different types for interconnecting the processors, resources are allocated by: receiving a plurality of software processes, each process having a connection requirement; receiving an allocation scheme, in which each of the software processes is allocated to a respective processor of the plurality of processors; determining a plurality of communication requirements based on the connection requirements and the processors to which each process is allocated; and for each of the communication requirements: determining the respective processors to which the associated processes have been assigned; and allocating a communications resource of a type that is suitable based on the categories of said respective processors, such that the total allocated communications resource does not exceed the predetermined communication resources.

Abstract: There is provided a method of generating information for a software system for use in a debug information database, the software system being defined in a low-level program code, the method comprising constructing a representation of the software system from the low-level program code; examining the representation to identify predetermined patterns; and generating a database of debug information for the software system from the results of the step of examining.