Patents by Inventor Daniel Tuers
Daniel Tuers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11763905Abstract: Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.Type: GrantFiled: December 16, 2021Date of Patent: September 19, 2023Assignee: Western Digital Technologies, Inc.Inventors: Grishma Shah, Sergey Anatolievich Gorobets, Daniel Tuers
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Patent number: 11755211Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: GrantFiled: October 3, 2022Date of Patent: September 12, 2023Assignee: Western Digital Technologies, Inc.Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Publication number: 20230197176Abstract: Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Applicant: Western Digital Technologies, Inc.Inventors: Grishma Shah, Sergey Anatolievich Gorobets, Daniel Tuers
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Publication number: 20230022998Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Patent number: 11487446Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: GrantFiled: February 12, 2021Date of Patent: November 1, 2022Assignee: Western Digital Technologies, Inc.Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Publication number: 20220179568Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.Type: ApplicationFiled: February 12, 2021Publication date: June 9, 2022Inventors: Grishma Shah, Daniel Tuers, Sahil Sharma, Hua-Ling Cynthia Hsu, Yenlung Li, Min Peng
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Patent number: 10592122Abstract: A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.Type: GrantFiled: March 31, 2015Date of Patent: March 17, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Abhijeet Manohar, Daniel Tuers, Sathyanarayanan Subramanian, Judah Gamliel Hahn
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Patent number: 10514748Abstract: Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.Type: GrantFiled: September 27, 2017Date of Patent: December 24, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Reed P. Tidwell, Yoav Weinberg, Daniel Tuers, Matthew Davidson, Eran Erez
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Publication number: 20190094938Abstract: Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Reed P. Tidwell, Yoav Weinberg, Daniel Tuers, Matthew Davidson, Eran Erez
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Patent number: 10241704Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.Type: GrantFiled: July 31, 2017Date of Patent: March 26, 2019Assignee: SanDisk Technologies LLCInventors: Daniel Tuers, Abhijeet Manohar, Jonathan Hsu
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Patent number: 9978456Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.Type: GrantFiled: November 17, 2014Date of Patent: May 22, 2018Assignee: SanDisk Technologies LLCInventors: Anubhav Khandelwal, Dana Lee, Abhijeet Manohar, Henry Chin, Gautam Dusija, Daniel Tuers, Chris Avila, Cynthia Hsu
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Patent number: 9940271Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.Type: GrantFiled: April 10, 2017Date of Patent: April 10, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Daniel Tuers, Abhijeet Manohar, Yoav Weinberg, Milton Lourenco Barrocas
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Publication number: 20170329549Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.Type: ApplicationFiled: July 31, 2017Publication date: November 16, 2017Applicant: SanDisk Technologies LLC:Inventors: Daniel Tuers, Abhijeet Manohar, Jonathan Hsu
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Patent number: 9794341Abstract: A server system with one or more processors and memory sends a verification request, to a client device, to verify that the client device is storing a data block, where the verification request includes verification parameters. In response, the server system obtains from the client device a first verification value for the data block. The server system compares the first verification value with a second verification value for the data block, where the second verification value was previously computed, in accordance with the data block and the verification parameters, and stored by the server system. In accordance with a determination that the first verification value matches the second verification value, the server system confirms that the client device is storing the data block.Type: GrantFiled: September 24, 2014Date of Patent: October 17, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Abhijeet Manohar, Daniel Tuers
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Patent number: 9780809Abstract: A non-volatile memory system may include a tracking module that tracks logic values of bits to be stored in memory elements identified as unreliable. A record of the logic values may be generated. During decoding of the data, a log likelihood ratio module may use the record to assign log likelihood ratio values for the decoding.Type: GrantFiled: April 30, 2015Date of Patent: October 3, 2017Assignee: SanDisk Technologies LLCInventors: Daniel Tuers, Abhijeet Manohar, Sujeeth Joseph
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Patent number: 9720612Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.Type: GrantFiled: April 30, 2015Date of Patent: August 1, 2017Assignee: SanDisk Technologies LLCInventors: Daniel Tuers, Abhijeet Manohar, Jonathan Hsu
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Publication number: 20170212849Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Daniel Tuers, Abhijeet Manohar, Yoav Weinberg, Milton Lourenco Barrocas
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Patent number: 9626106Abstract: Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.Type: GrantFiled: January 13, 2015Date of Patent: April 18, 2017Assignee: SanDisk Technologies LLCInventors: Jonathan Hsu, Daniel Tuers, Tien-chien Kuo
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Patent number: 9626286Abstract: A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully perform them.Type: GrantFiled: October 3, 2014Date of Patent: April 18, 2017Assignee: SanDisk Technologies LLCInventors: Sergey Anatolievich Gorobets, Matthew Davidson, Gary J. Lin, Daniel Tuers, Robert Jackson
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Patent number: 9620182Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.Type: GrantFiled: December 31, 2013Date of Patent: April 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Daniel Tuers, Abhijeet Manohar, Yoav Weinberg, Milton Lourenco Barrocas