Abstract: In an embodiment, a computer system comprises one or more co-packaged integrated circuits having a communication fabric that couples various agent circuits. The agent circuits transmit packets via the communication fabric, which can include command-data packets and command packets. In various embodiments, the communication fabric includes an arbitration circuit to arbitrate among packets to transmit on the fabric. The arbitration circuit may select a winning packet from one or more packets during an arbitration cycle based on a history of previously selected packets. The arbitration circuit may selectively implement, upon receiving a command packet and a command-data packet during a particular arbitration cycle and based on frequencies of particular buses of the communication fabric, one of at least two different arbitration schemes to select a winning packet for the arbitration cycle when an immediately preceding attribution cycle has no winning packet.

Abstract: A computer system includes a power management circuit (PMC) that is configured to receive a set of one or more performance state requests from one or more requestors. The PMC is also configured to permit, based on the set of one or more performance state requests, a transition to an internal performance state having at least one component performance state not specified externally to the PMC as being available to the one or more requestors. The PMC is further configured to implement transitioning to the internal performance state by causing a change to operation of a particular circuit of the computer system that is not defined at the interface to the PMC. The particular circuit may be a clock signal that crosses a boundary between first and second power domains of the computer system in one implementation. The PMC may also implement performance state pinning in some implementations.

Abstract: In an embodiment, a computer system comprises one or more co-packaged integrated circuits having a communication fabric that couples various agent circuits. The agent circuits transmit packets via the communication fabric, which can include command-data packets and command packets. In various embodiments, the communication fabric includes an arbitration circuit to arbitrate among packets to transmit on the fabric. The command-data packets may be allocated to a first plurality of virtual channels while the command packets are allocated to a second plurality of virtual channels. The arbitration circuit may arbitrate among the first plurality of virtual channels to select a command-data packet and the second plurality of virtual channels to select a command packet. The arbitration circuit may then arbitrate between the selected command-data packet and the selected command packet to select a winning packet to transmit based on a history of previously selected packets.

Abstract: A system includes a power management processor that may be configured to monitor operation of one or more circuit blocks in the system, and to determine a particular performance state of a set of performance states for one or more power domains in the system based on the monitored operation. The system further includes a performance management circuit that may be configured to receive, from the power management processor, an indication of the particular performance state. The performance management circuit may further be configured to determine a transition path from a current performance state to the particular performance state that avoids illegal performance state transitions, and to cause a control circuit to transition to the particular performance state using the transition path.

Abstract: An apparatus includes a communication fabric, a plurality of agent circuits, a performance management circuit (PMC), and a debug circuit. The communication fabric may transfer transactions from source circuits to destination circuits. The agent circuits may issue real-time (RT) transactions in accordance with a current available bandwidth of the communication fabric. The PMC may allocate, based on the current available bandwidth, respective bandwidth usage targets to ones of the agent circuits. The debug circuit may access operational states of the agent circuits. A given one of the agent circuits may also, based on a determination that the respective bandwidth usage target is insufficient for current activity, capture a set of current values from one or more registers in the given agent circuit without affecting a state of the registers. The given agent circuit may then send at least a portion of the set of current values to the debug circuit.

Abstract: In an embodiment, a computer system comprises one or more co-packaged integrated circuits having a communication fabric that couples various agent circuits. The agent circuits transmit packets via the communication fabric, which can include command-data packets and command packets. In various embodiments, the communication fabric includes an arbitration circuit to arbitrate among packets to transmit on the fabric. The arbitration circuit may select a winning packet from one or more packets during an arbitration cycle based on a history of previously selected packets. The arbitration circuit may selectively implement, upon receiving a command packet and a command-data packet during a particular arbitration cycle and based on frequencies of particular buses of the communication fabric, one of at least two different arbitration schemes to select a winning packet for the arbitration cycle when an immediately preceding attribution cycle has no winning packet.

Abstract: In an embodiment, a computer system comprises one or more co-packaged integrated circuits having a communication fabric that couples various agent circuits. The agent circuits transmit packets via the communication fabric, which can include command-data packets and command packets. In various embodiments, the communication fabric includes an arbitration circuit to arbitrate among packets to transmit on the fabric. The command-data packets may be allocated to a first plurality of virtual channels while the command packets are allocated to a second plurality of virtual channels. The arbitration circuit may arbitrate among the first plurality of virtual channels to select a command-data packet and the second plurality of virtual channels to select a command packet. The arbitration circuit may then arbitrate between the selected command-data packet and the selected command packet to select a winning packet to transmit based on a history of previously selected packets.

Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

Abstract: An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.

Abstract: In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.

Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.

Abstract: An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.

Abstract: In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.

Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.

Abstract: In some embodiments, a system includes a plurality of processor cores connected to an energy source. The system further includes one or more budget creation circuits configured to determine respective portions of a total credit budget of the energy source. The system further includes a plurality of credit distribution circuits configured to distribute the respective portions of the total credit budget to respective subsets of the processor cores. The credit distribution circuits share energy credits in response to determining that at least some energy credits will be unused. As a result, energy credits are more likely to be used by the processor cores, as compared to a system where the energy credits are not shared.

Abstract: In some embodiments, a processor core includes an energy tracking circuit and an execution management circuit. The energy tracking circuit is configured to determine an amount of remaining allocated energy of the processor core. The execution management circuit is configured to make a determination whether to stall execution of one or more pipeline operations at the processor core based on a comparison of the amount of remaining allocated energy to a stall threshold. The determination involves applying one or more pseudo-random components to the amount of remaining allocated energy, the stall threshold, or both. The determination is made such that the smaller the amount of remaining allocated energy, the more likely the execution of one or more instructions is to be stalled.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract: Embodiments of a computing system that may monitor energy usage are disclosed. The embodiments may provide a low overhead method for determining energy usage of a given application or process. Circuitry is configured to determine a respective energy for each of the plurality of operations and sum each respective energy for at least some of the plurality of operations to generate a normalized total. The circuitry may be further configured to scale the normalized total to generate an energy value, and store the energy value in a register. System software may then read the energy value from the register and determine an energy usage for at least one application dependent upon the energy value.

Abstract: In some embodiments, a system includes a plurality of processor cores and a credit distribution circuit. The credit distribution circuit is configured to provide credits to the processor cores. A quantity of the provided credits is based on a total credit budget and requests for additional credits corresponding to the processor cores. The total credit budget is based on an amount of energy available to the processor cores (e.g., made available by a power supply) during a particular window of time. A particular processor core is configured to determine, based on a remaining number of credits for the particular processor core, whether to perform one or more pipeline operations. The particular processor core is further configured to deduct, based on determining to perform the one or more pipeline operations, one or more credits from a remaining quantity of credits allocated to the particular processor core.