Patents by Inventor Daniel W. Dobberpuhl
Daniel W. Dobberpuhl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8134356Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.Type: GrantFiled: March 11, 2011Date of Patent: March 13, 2012Assignee: Apple Inc.Inventors: Daniel W. Dobberpuhl, Vincent R. von Kaenel
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Publication number: 20110156693Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.Type: ApplicationFiled: March 11, 2011Publication date: June 30, 2011Inventors: Daniel W. Dobberpuhl, Vincent R. von Kaenel
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Patent number: 7928747Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.Type: GrantFiled: December 9, 2009Date of Patent: April 19, 2011Assignee: Apple Inc.Inventors: Daniel W. Dobberpuhl, Vincent R. von Kaenel
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Publication number: 20100085031Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.Type: ApplicationFiled: December 9, 2009Publication date: April 8, 2010Inventors: Daniel W. Dobberpuhl, Vincent R. von Kaenel
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Patent number: 7652494Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.Type: GrantFiled: May 25, 2007Date of Patent: January 26, 2010Assignee: Apple Inc.Inventors: Daniel W. Dobberpuhl, Vincent R. von Kaenel
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Patent number: 7372323Abstract: In one embodiment, an integrated circuit comprises resonance limiter circuits coupled to a power supply connection of the integrated circuit. The resonance limiter circuits are configured to detect oscillation on the power supply connection at a resonant frequency, and to dampen the resonant frequency oscillation responsive to detecting the oscillation. In some embodiments, the resonance limiter circuits may damp oscillation at or above the resonant frequency or approximately the resonant frequency (e.g. somewhat below the resonance frequency). The resonant frequency depends on a package of the integrated circuit. In an embodiment, a resonance limiter circuit comprises a filter and a transistor coupled in parallel with the filter between a power supply connection and a ground connection. The filter is tuned to approximately a resonant frequency (e.g. the lowest resonant frequency) that depends on a package corresponding to an integrated circuit into which the resonance limiter circuit is fabricated.Type: GrantFiled: July 26, 2006Date of Patent: May 13, 2008Assignee: P.A. Semi, Inc.Inventors: Vincent R. von Kaenel, Daniel W. Dobberpuhl
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Patent number: 7320022Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: GrantFiled: July 25, 2002Date of Patent: January 15, 2008Assignee: Broadcom CorporationInventors: Mark D. Hayter, Shailendra S. Desai, Daniel W. Dobberpuhl, Kwong-Tak A. Chui
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Publication number: 20070257721Abstract: In one embodiment, an integrated circuit comprises resonance limiter circuits coupled to a power supply connection of the integrated circuit. The resonance limiter circuits are configured to detect oscillation on the power supply connection at a resonant frequency, and to dampen the resonant frequency oscillation responsive to detecting the oscillation. In some embodiments, the resonance limiter circuits may damp oscillation at or above the resonant frequency or approximately the resonant frequency (e.g. somewhat below the resonance frequency). The resonant frequency depends on a package of the integrated circuit. In an embodiment, a resonance limiter circuit comprises a filter and a transistor coupled in parallel with the filter between a power supply connection and a ground connection. The filter is tuned to approximately a resonant frequency (e.g. the lowest resonant frequency) that depends on a package corresponding to an integrated circuit into which the resonance limiter circuit is fabricated.Type: ApplicationFiled: July 26, 2006Publication date: November 8, 2007Applicant: P.A. Semi, Inc.Inventors: Vincent R. von Kaenel, Daniel W. Dobberpuhl
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Patent number: 7287649Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: GrantFiled: May 18, 2001Date of Patent: October 30, 2007Assignee: Broadcom CorporationInventors: Mark D. Hayter, Shailendra S. Desai, Daniel W. Dobberpuhl, Kwong-Tak A. Chui
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Patent number: 7276925Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.Type: GrantFiled: July 1, 2005Date of Patent: October 2, 2007Assignee: P.A. Semi, Inc.Inventors: Daniel W. Dobberpuhl, Vincent R. von Kaenel
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Patent number: 6952791Abstract: A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may use a write pointer and a read pointer which may be clocked by two different clocks allowing independent write and read accesses to the buffer. In an initialization mode, a predetermined pattern of data may be written into an entry in the buffer. In one embodiment, a logic circuit may detect the predetermined pattern of data and may cause the value of the write pointer to be captured. A synchronizing circuit may synchronize an indication that the predetermined pattern of data has been detected to the clock used by the read pointer. The synchronizer circuit may then provide a initialize signal to the read pointer which stores the captured write pointer value into the read pointer.Type: GrantFiled: January 11, 2002Date of Patent: October 4, 2005Assignee: Broadcom CorporationInventors: James B. Keller, Daniel W. Dobberpuhl
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Patent number: 6671216Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.Type: GrantFiled: January 22, 2003Date of Patent: December 30, 2003Assignee: Broadcom CorporationInventors: Robert Rogenmoser, Steve T. Nishimoto, Daniel W. Dobberpuhl
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Patent number: 6657462Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.Type: GrantFiled: January 22, 2003Date of Patent: December 2, 2003Assignee: Broadcom CorporationInventor: Daniel W. Dobberpuhl
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Publication number: 20030117186Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.Type: ApplicationFiled: January 22, 2003Publication date: June 26, 2003Applicant: Broadcom Corp.Inventor: Daniel W. Dobberpuhl
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Publication number: 20030107933Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.Type: ApplicationFiled: January 22, 2003Publication date: June 12, 2003Inventors: Robert Rogenmoser, Steve T. Nishimoto, Daniel W. Dobberpuhl
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Publication number: 20030105985Abstract: A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may use a write pointer and a read pointer which may be clocked by two different clocks allowing independent write and read accesses to the buffer. In an initialization mode, a predetermined pattern of data may be written into an entry in the buffer. In one embodiment, a logic circuit may detect the predetermined pattern of data and may cause the value of the write pointer to be captured. A synchronizing circuit may synchronize an indication that the predetermined pattern of data has been detected to the clock used by the read pointer. The synchronizer circuit may then provide a initialize signal to the read pointer which stores the captured write pointer value into the read pointer.Type: ApplicationFiled: January 11, 2002Publication date: June 5, 2003Inventors: James B. Keller, Daniel W. Dobberpuhl
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Publication number: 20030058019Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.Type: ApplicationFiled: May 1, 2002Publication date: March 27, 2003Inventor: Daniel W. Dobberpuhl
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Patent number: 6538943Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.Type: GrantFiled: June 17, 2002Date of Patent: March 25, 2003Assignee: Broadcom CorporationInventors: Robert Rogenmoser, Steve T. Nishimoto, Daniel W. Dobberpuhl
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Patent number: 6535036Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.Type: GrantFiled: May 1, 2002Date of Patent: March 18, 2003Assignee: Broadcom CorporationInventor: Daniel W. Dobberpuhl
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Publication number: 20020174252Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: ApplicationFiled: May 18, 2001Publication date: November 21, 2002Applicant: Broadcom CorporaionInventors: Mark D. Hayter, Shailendra S. Desai, Daniel W. Dobberpuhl, Kwong-Tak A. Chui