Abstract: Present embodiments provide various open coil spring assemblies which perform like an encased spring assembly. The embodiments have elastic lacings or connections which connect springs to springs or springs to lacings. Various spring embodiments are provided as well as various arrangements for the elastic lacings. All of these features improve compliance and stability while reducing motion transfer.

Abstract: Present embodiments provide various open coil spring assemblies which perform like an encased spring assembly. The embodiments have elastic lacings or connections which connect springs to springs or springs to lacings. Various spring embodiments are provided as well as various arrangements for the elastic lacings. All of these features improve compliance and stability while reducing motion transfer.

Abstract: Present embodiments provide various open coil spring assemblies which perform like an encased spring assembly. The embodiments have elastic lacings or connections which connect springs to springs or springs to lacings. Various spring embodiments are provided as well as various arrangements for the elastic lacings. All of these features improve compliance and stability while reducing motion transfer.

Abstract: Present embodiments provide various open coil spring assemblies which perform like an encased spring assembly. The embodiments have elastic lacings or connections which connect springs to springs or springs to lacings. Various spring embodiments are provided as well as various arrangements for the elastic lacings. All of these features improve compliance and stability while reducing motion transfer.

Abstract: Present embodiments provide various open coil spring assemblies which perform like an encased spring assembly. The embodiments have elastic lacings or connections which connect springs to springs or springs to lacings. Various spring embodiments are provided as well as various arrangements for the elastic lacings. All of these features improve compliance and stability while reducing motion transfer.

Abstract: An orthopedic device and method for correcting angular deformation of a bone structure having a growth plate. The device includes first and second hinge members connected together at a hinge joint. The device is adapted for mounting the orthopedic device to the bone structure with the pivot joint positioned over the growth plate. Alignment of the pivot joint with the growth plate promotes asymmetric growth of the growth plate to thereby correct the angular deformation.

Abstract: There is disclosed an operand queue for use in a floating point unit. The floating point unit comprises floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also comprises an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand being written to an external memory by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units subsequent to the execution of the floating point write instruction.

Abstract: A system and method for securing an intramedullary rod in a medullary canal of a long bone is provided. The system includes an intramedullary rod and a screw assembly for receiving the rod. The screw assembly has a transverse receiving bore for receiving the intramedullary rod and a securing member movable toward the bore for securing the rod to the screw assembly. An alignment jig may also be provided for aligning the rod with the receiving bore during installation.

Abstract: An orthopedic device and method for correcting angular deformation of a bone structure having a growth plate. The device includes first and second hinge members connected together at a hinge joint. The device is adapted for mounting the orthopedic device to the bone structure with the pivot joint positioned over the growth plate. Alignment of the pivot joint with the growth plate promotes asymmetric growth of the growth plate to thereby correct the angular deformation.

Abstract: A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an exponent portion of a standard length from a source without the FPU and transforms the denormal number into a normalized number having an exponent portion of an expanded length greater than the standard length, (2) a floating point execution core, coupled to the load unit, that processes the normalized number at least once to yield a processed normalized number, the expanded length of the exponent portion allowing the processed normalized number to remain normal during processing thereof and (3) a store unit, coupled to the floating point execution core, that receives the processed normalized number and transforms the processed normalized number back into a denormal number having an exponent portion of the standard length.

Abstract: There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also comprises a split array for adding the partial products. A first summation array comprises a first group of adders that sum the even partial products to produce an even summation value. A second summation array comprises a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.

Abstract: A floating point unit includes floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also includes an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand written by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units when the first operand is committed or virtually committed.

Abstract: A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an exponent portion of a standard length from a source without the FPU and transforms the denormal number into a normalized number having an exponent portion of an expanded length greater than the standard length, (2) a floating point execution core, coupled to the load unit, that processes the normalized number at least once to yield a processed normalized number, the expanded length of the exponent portion allowing the processed normalized number to remain normal during processing thereof and (3) a store unit, coupled to the floating point execution core, that receives the processed normalized number and transforms the processed normalized number back into a denormal number having an exponent portion of the standard length.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

Abstract: A multiplier circuit for use in a data processor. The multiplier circuit contains a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also contains a split array for adding the partial products. A first summation array has a first group of adders that sum the even partial products to produce an even summation value. A second summation array has a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous.

Abstract: There is disclosed, for use in a processing device having an N-way set associative data array (such as an L1 cache), a built-in self-test (BIST) circuit for testing the validity of storage locations in the data array. The BIST circuit comprises 1) a memory capable of storing a test program executable by the processing device, wherein the test program is capable of testing the validity of the storage locations in the data array; and 2) a controller capable of copying the test program from the memory into first selected storage locations in a first way in the data array, wherein the processing device executes the copied test program stored in the first selected storage locations subsequent to the copying to thereby test the validity of second selected storage locations in at least one of the N ways.

Abstract: There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address stored in the TLB and that makes the region configuration bits available at the same time that the physical address is generated/translated by the TLB. The TLB comprises: 1) a tag array capable of storing an untranslated address in one of N tag entries in the tag array; 2) a data array capable of storing a translated physical address corresponding to the untranslated address in one of N data entries in the data array; and 3) a region configuration array capable of storing region configuration bits associated with the translated physical address in one of N region configuration entries in the region configuration array.