Patents by Inventor Daniel W. Krueger

Daniel W. Krueger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7215581
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: May 8, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan P Lotz, Daniel W. Krueger, Manuel Cabanas-Holmen
  • Patent number: 7179690
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: February 20, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan P Lotz, Daniel W. Krueger, Manuel Cabanas-Holmen
  • Patent number: 7054203
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: May 30, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan P Lotz, Daniel W. Krueger, Manuel Cabanas-Holmen
  • Patent number: 6937527
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: August 30, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan P Lotz, Daniel W. Krueger, Manuel Cabanas-Holmen
  • Patent number: 6930527
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: August 16, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Manuel Cabanas-Holmen, Daniel W. Krueger, Jonathan P Lotz
  • Patent number: 6882201
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: April 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kenneth Koch, II, Manuel Cabanas-Holmen, Daniel W. Krueger
  • Publication number: 20020129293
    Abstract: The present invention bundles four ring oscillators, a 20-bit ripple counter and the necessary control logic needed to implement a JTAG scan based interface. The present system can be located on every die, so that each location can be individually tested. It communicates with the outside world through a standard JTAG interface. It is accessible at wafer, package, and system test which allows for several methods of correlating the oscillator speed to the speed of a part in the actual system.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 12, 2002
    Inventors: John F. Hutton, William A. Hudson, Daniel L. Halperin, Daniel W. Krueger, Jack T. Lavier, Mark D. Musgrove