Abstract: A system for monitoring the orientation and position of components in an oil well. The system includes a first well component, a second well component, and a transducer attached to the first well component, for generating a pulse. The system also includes a transceiver attached to the second well component for measuring the parameters of the pulse generated by the transducer, and a processor in communication with the transceiver that receives information about the parameters of the pulse as measured by the transceiver, and that calculates the position of the transceiver relative to the transducer.

Abstract: A system for monitoring the orientation and position of components in an oil well The system includes a first well component a second well component, and a transducer attached to the first well component, for generating a pulse. The system also includes a transceiver attached to the second well component for measuring the parameters of the pulse generated by the transducer, and a processor in communication with the transceiver that receives information about the parameters of the pulse as measured by the transceiver, and that calculates the position of the transceiver relative to the transducer.

Abstract: A reversible four cycle internal combustion engine. A crankshaft is rotatably mounted in a block and a piston is operatively mounted to a crankshaft via a connecting rod. A follower wheel traverses a cam as the cam rotates with the crankshaft, and in doing so, causes a combustion chamber valve to open and close access of an intake port in the block and an exhaust port in the block to a combustion chamber in the block so as to allow the engine to achieve each of a power stroke thereof, a exhaust stroke thereof, a intake stroke thereof, and a compression stroke thereof.

Abstract: A system and method for controlling and monitoring an industrial controller using a portable wireless device. The system includes a programmable logic controller (PLC), a local server for exchanging communication with the PLC, a Internet Service Provider (ISP) server for exchanging communication with the local server using the Internet, and a wireless user communication device for exchanging communication with the ISP server. A user utilizes the Internet to monitor the operation of the PLC and input control commands to the PLC using the wireless user communication device.

Abstract: In one aspect, the invention is a method for communicating with a device such as a programmable logic controller (PLC) or an I/O device. The method includes steps of: interconnecting the device to a personal computer (PC) running a web browser; and running an application on the PC that launches the web browser to an initial page and uploads a web browser applet or active x object from the device to the PC via the interconnection. The above-described embodiment combines PLC and/or I/O communications with the Internet's wide reach and ability to supply information, and does so with the “look and feel” of a PC-Internet interface without adding significantly to the overhead burden of these small devices.

Abstract: A system and method for establishing communications in a power plant comprises a power generation system having an interface for establishing wireless communication, at least one power plant auxiliary system having an interface for enabling wireless communication, and a wireless communications link, having at least two redundant wireless communications channels, established between the power generation system and the power plant auxiliary system. The two redundant wireless communications channels may be two redundant wireless radio frequency channels. The communications link may be established utilizing a network communications controller which wirelessly communicates with the power generation system and the power plant auxiliary system. One or more of the power plant auxiliary systems may communicate with the network communications controller through a repeater.

Abstract: A system and method for controlling and monitoring an industrial controller using a portable wireless device. The system includes a programmable logic controller (PLC), a local server for exchanging communication with the PLC, a Internet Service Provider (ISP) server for exchanging communication with the local server using the Internet, and a wireless user communication device for exchanging communication with the ISP server. A user utilizes the Internet to monitor the operation of the PLC and input control commands to the PLC using the wireless user communication device.

Abstract: The present invention is a communication unit for exchanging data. More specifically, the unit includes an initiator and a responder that exchange data with a single time base. In one embodiment, the initiator generates a time base output signal that is used for determining a multiple of the rate at which data will be transferred to the responder. When data is received from the responder, the time base signal is used to over-sample the data to determine the point at which the data from the responder is valid.

Abstract: A programmable logic controller is provided in which I/O modules situated in respective slots are coupled to a CPU by a main bus including a serial data line. A dedicated slot enable line is provided from the CPU interrupt controller to each slot into which an I/O module may be positioned. In this manner, the CPU can enable a selected I/O module when desired. The I/O module includes an interrupt feature wherein an interrupt signal is provided to the same slot enable line which communicates a slot enable signal to the I/O module. The I/O module returns an interrupt on the slot enable line at times other than when the slot enable line is being used by the CPU interrupt controller to send a slot enable signal. The CPU interrupt controller includes an interrupt detection circuit which makes a determination of when two conditions simultaneously occur, namely when both a particular slot enable line is active and the CPU is not enabling the corresponding slot with the slot enable signal.

Abstract: An apparatus and method are provided for preventing the runaway of the integral term of a proportional integral differential controller which is usable in a feedback system. An error signal is supplied to the controller by the feedback system. The controller produces a control variable output signal from the error signal. In accordance with the invention, the controller imposes a slew rate limit on the control variable output signal. Also in accordance with the invention, whenever the controller attempts to drive the control variable output signal to exceed the slew rate limit, the integral term associated with the controller is adjusted to a value which forces the control variable output signal to its slew rate limited value. In this manner, runaway of the integral term associated with the controller is desirably avoided.

Abstract: A method is provided for communicating among a plurality of programmable logic controllers (PLC's) coupled together on a common bus. A master PLC and a plurality of slave PLC's are coupled to the bus. An attach signal is transmitted by the master PLC to address and select the particular slave PLC to which the master PLC desires to transmit a message. The master PLC then transmits a mailbox signal including data and message length information regarding a next message if not all data from the master PLC and intended for the slave PLC could fit in the mailbox message. Additional next messages, each including data and next message length information, are sent by the master PLC to the selected slave PLC as necessary until all of the data intended for the selected slave PLC is transmitted by the master PLC.

Abstract: A programmable logic controller is provided which includes a function block processor for processing function block instructions and a bit processor for processing Boolean instructions. The bit processor decodes and identifies the OPCODE of each instruction command in a user program memory and returns control to the function block processor if at least one of the following two conditions occurs, namely, 1) there is power flow in the power flow register of the bit processor and 2) the function block is one which must be executed by the function block processor. The bit processor waits until the function block processor has retrieved the instruction pointer from the bit processor and then adjusts the instruction pointer to point to the next OPCODE in the user program memory.

Abstract: A method is provided by which a programmable logic controller checks each statement of an instruction list (IL) program to determine if any such statement or the order of statements violates one of a set of syntax rules which are stored in a memory in the controller. If a rule violation is found, an error indication is generated to signify that the particular IL program under test by the controller can not be accurately converted or translated into a relay ladder diagram. However, if no rule violation is found by the controller, then the controller accepts the IL program.

Abstract: A method is provided for configuring a smart module which is coupled to a programmable logic controller. The controller includes an initial configuration file which specifies an initial configuration for the smart module. After power up and initialization of the controller, the initial configuration file is transmitted from the controller to the smart module. The initial configuration file is now designated a current configuration file and the smart module assumes the configuration specified by the current configuration file. In accordance with the method of the invention, module specific information which is stored in the module is then displayed to aid a user in configuring the module. The user can then modify the current configuration file in response to the module specific information which was displayed. This method significantly simplifies the process of configuring smart modules for the user.

Abstract: A signal processing apparatus is provided for recovering the clock signal and data signal from an encoded information signal. The encoded signal which is to be processed includes first symbols exhibiting a first frequency representing logical ones and second symbols exhibiting a second frequency representing logical zeros. A tapped delay line produces a first recovered clock signal exhibiting a frequency approximately twice that of the clock rate of the data signal. Circuitry is provided for recovering the data signal and a second recovered clock signal which exhibits a frequency approximately equal to the clock rate of the data signal.

Abstract: An electronic processor based system is provided which is capable of receiving plug-in cards. The plug-in card includes a memory which contains a first error check word which is a function of seed data words which are also stored in that memory. The first error check word is related to the seed data words by a predetermined algorithm. When the card is inserted in the processor system, the system reads the first error check word and the seed data words stored in the memory on the card. In one form, the processor system then performs its own independent calculation of a second error check word by using the same predetermined algorithm to operate on the seed data words retrieved from the card. The processor system compares the second error check word with the retrieved first error check word. If the second error check word is found to be the same as the retrieved first error check word, then the card is permitted to continue operation together with the system.

Abstract: A carrier detection circuit is provided for reliably detecting the presence of a carrier signal. The carrier detection circuit operates on a carrier signal which includes a first symbol exhibiting a first frequency representing a logic 1 and a second symbol exhibiting a second frequency representing a logic 0. A first carrier detect pulse exhibiting a first logic state is generated each time the carrier signal exceeds a predetermined threshold voltage. A plurality of consecutive first carrier detect pulses are checked to determine the logic state of each. A second carrier detect pulse is generated if it is determined that each of the plurality of consecutive first carrier detect pulses exhibit the first logic state.

Abstract: For use in a communications system in which a plurality of communication devices are connected to a plurality of buses in a redundant communication type system in which the same data is concurrently transmitted between the communication devices over the plurality of buses, a scheme determines which of the buses should be utilized for the reception of data through the examination of each of the buses for the existence of transmitted data. Upon determining that data is present on any of the buses, there is established a first period of time which terminates a fixed increment of time after data is absent from all of the buses. An indication is then provided for each bus which has data thereon during said first period of time and extending at least through a second fixed increment of time beyond that first period of time.

Abstract: A sine wave generator circuit for providing, as its output, a substantially perfect sine wave signal includes a multiplier responsive to first input and second input signals of varying magnitude for providing as its output the sine wave signal as a function of the two input signals. There is further included a first feedback circuit path connected between the output and one of the inputs of the multiplier which includes a resistance-capacitance network for providing a phase delayed representation of the output signal as the first of the input signals. The amount of phase delay is determined by the relative values of the resistance-capacitance network and determines the frequency of the sine wave output. Further included is a reference signal the magnitude of which will determine the magnitude of the sine wave output signal. The reference signal is applied to a second feedback circuit path connected between the multiplier output and the other one of its inputs.