Patents by Inventor Daniel W. Storaska
Daniel W. Storaska has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8401135Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.Type: GrantFiled: February 2, 2010Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska
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Patent number: 8183949Abstract: A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.Type: GrantFiled: February 5, 2009Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Daniel W. Storaska, Michael A. Sorna
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Patent number: 8183950Abstract: A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO.Type: GrantFiled: February 5, 2009Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Daniel W. Storaska, Michael A. Sorna
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Patent number: 8040813Abstract: An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.Type: GrantFiled: June 2, 2005Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
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Patent number: 8024679Abstract: A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss.Type: GrantFiled: December 6, 2007Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
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Publication number: 20110188566Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.Type: ApplicationFiled: February 2, 2010Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska
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Patent number: 7869544Abstract: An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.Type: GrantFiled: January 3, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Michael A. Sorna, William R. Kelly, Daniel W. Storaska
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Publication number: 20100194482Abstract: A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.Type: ApplicationFiled: February 5, 2009Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel W. Storaska, Michael A. Sorna
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Publication number: 20100194483Abstract: A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO.Type: ApplicationFiled: February 5, 2009Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: DANIEL W. STORASKA, MICHAEL A. SORNA
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Publication number: 20090261890Abstract: An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Inventors: John A. Fifield, Bradford Hunter, Todd M. Rasmus, Michael A. Sorna, Daniel W. Storaska
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Publication number: 20090175325Abstract: An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.Type: ApplicationFiled: January 3, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Sorna, William R. Kelly, Daniel W. Storaska
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Publication number: 20090146692Abstract: A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Inventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
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Patent number: 7352815Abstract: Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.Type: GrantFiled: June 23, 2003Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Hibourahima Camara, Joseph Natonio, Karl D. Selander, Michael A. Sorna, Jeremy K. Stephens, Daniel W. Storaska
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Patent number: 7265433Abstract: A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.Type: GrantFiled: January 13, 2005Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: Edward R. Pillai, Louis L. Hsu, Wolfgang Sauter, Daniel W. Storaska
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Patent number: 7145413Abstract: As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.Type: GrantFiled: June 10, 2003Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Joseph Natonio, Daniel W. Storaska, William F. Washburn
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Publication number: 20040258166Abstract: Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.Type: ApplicationFiled: June 23, 2003Publication date: December 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hibourahima Camara, Joseph Natonio, Karl D. Selander, Michael A. Sorna, Jeremy K. Stephens, Daniel W. Storaska
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Publication number: 20040251983Abstract: As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.Type: ApplicationFiled: June 10, 2003Publication date: December 16, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. Hsu, Joseph Natonio, Daniel W. Storaska, William F. Washburn
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Patent number: 6775736Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.Type: GrantFiled: January 31, 2002Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Rajiv J. Joshi, Jeremy K. Stephens, Daniel W. Storaska
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Patent number: 6751152Abstract: A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used.Type: GrantFiled: October 31, 2001Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Toshiaki K. Kirihata, Daniel W. Storaska
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Patent number: 6711078Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.Type: GrantFiled: July 1, 2002Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Ciaran J. Brennan, John A. Fifield, Jeremy K. Stephens, Daniel W. Storaska