Abstract: An optical disk system is presented which incorporates computer graphics rendering capability to create and display three-dimensional (3-D) objects synchronized with 3-D sound. The optical disk system includes an audio/video (A/V) decoder coupled to a microprocessor and a rendering unit. The A/V decoder and the microprocessor receive a bitstream including encoded video and audio data, 3-D presentation data, and navigation data. The 3-D presentation data includes object and audio modeling data, and may also include instructions executed by the microprocessor in order to perform an operation upon the object and audio modeling data. The object modeling data includes data pertaining to an object to be displayed upon a display device, and the audio modeling data includes data pertaining to sound to be produced by multiple speakers. The bitstream may be a DVD-compliant bitstream having an sub-picture unit (SPU) portion, and the 3-D presentation data may be conveyed using the SPU portion of the bitstream.

Abstract: An apparatus comprising a plurality of register logic circuits, a core circuit, a memory circuit, and a plurality of logic circuits. The register logic circuits may each be configured to generate a first logic signal in response to (i) an input data signal, (ii) a second logic signal, (iii) a first clock signal and (iv) a second clock signal. The core circuit may be configured to generate a plurality of data signals and a first control signal in response to the first logic signals and a second control signal. The memory may be configured to present the second control signal to the core circuit. The logic circuits may each be configured to present the second logic signal in response to the first logic signal and the data signals. An embedded FPGA core may be enabled to provide an interconnect to a chip. Additionally, software may enable a wide variety of features including bug fixes and product variations, all without changing the silicon.

Abstract: A system for silicon chip evaluation comprising a chip embedded in a wafer and one or more testbench circuits embedded in the wafer, wherein the one or more testbenches provide verification of the chip. One aspect of the present invention concerns a method for silicon chip verification comprising the steps of (A) embedding a chip in a silicon wafer, (B) embedding one or more testbench circuits in the silicon wafer, and (C) communicating between the one or more testbenches and the chip to provide silicon verification of the chip.

Abstract: The present invention is directed to a system and method for repairing degraded data. In a first aspect of the present invention, a method for patching degraded video data includes receiving a first frame of video data and decoding the first frame of video data so as to enable the first frame of video data to be displayed on a display device. A portion of the decoded first frame of video data that is degraded is identified. The degraded portion of the first frame of video data is patched utilizing a second portion of video data wherein the degraded portion of the first frame of video data is patched with the second portion of video data to enable the first frame of video data and the second portion of video data to be displayed concurrently. In a second aspect of the present invention, a video data patching apparatus includes a source decoder capable of accepting video data, the source decoder capable of decoding the video data so as to enable the video data to be displayed on a display device.

Abstract: An improved clock distribution system is provided for a multi block network having a series of independent blocks, with each independent block having an average load tap signal. The clock distribution circuit uses the load tap signal from the slowest independent block to synchronize the clock used in the remaining blocks. The clock for the subsequent block is tuned to the average load tap signal of the slowest block. The system clock system is incrementally delayed until it is in tuned with the average load tap signal of the slowest block, then if can be provided to the subsequent blocks of the network. The clock distribution system comprises sequential delay stages to incrementally delay the reference clock signal. The shift register controls each stage of delay, by enabling a multiplexer to allow the incrementally delayed reference clock signal to pass through.

Abstract: An apparatus comprising a drive server, a control server and one or more decoder devices. The drive server may be configured to present one or more compressed data streams in response to one or more first control signals. The control server may be configured to present one or more of the compressed data streams in response to (i) one or more request signals and (ii) the one or more compressed data streams. The decoder devices may be configured to present a decoded video signal and a decoded audio signal in response to (i) one or more second control signals and (ii) the one or more compressed data streams. The navigation software, which traditionally is processed local to the decoder, may be processed on the control server. The control server may be enabled to control the remote decoder.

Abstract: A graphical video editing system that allows manipulation of images for input to the video encoding and decoding process. The debugging of video encoders and decoders is aided by user controlled editing of problem areas in test images, and the graphical video editing system is coupled directly to the video encoder or decoder being debugged so that the effects of the editing can be immediately observed. This system advantageously provides a speedup in the debugging process by simplifying the detection of problem areas and providing a fast method for narrowing the possible causes of image flaws. Broadly speaking, the present invention contemplates a graphical video editing system for regeneration of bitstreams. The system comprises an encoder module, a decoder module, a display editor module and a display. The encoder module is configured to receive an input image and to convert the input image into an encoded bitstream.

Abstract: A host register interface testing system and method are disclosed. The system includes a host register unit including information that is indicative of a set of host registers corresponding to a programmable device under test. The system further includes a rule set unit including information that is indicative of constraints on values that the set of host registers may assume and a test setup generator configured to access the host register unit and the rule set unit and to generate a set of test setups based on the contents of the host register unit and the rule set unit where each test setup corresponds to a valid state of the set of host registers. In one embodiment, the test setup generator is suitable for applying a test setup from the set of test setups to the device under test. In one embodiment, the system may further include a verifier configured to receive the output of the device under test and, based thereon, for determining the functionality of the device under test.

Abstract: A system and method is provided for verifying the functionality of a multimedia device. In one embodiment, the system includes a device under test and a computer configured to test the device by providing test bitstreams and sequences of user actions to the device. The computer uses bitstream profiles to describe, edit, and generate multimedia bitstreams. The profiles are used to describe in human-intelligible form the values of fields of interest in multimedia bitstreams. Since the fields of interest vary between verification tests, the profile form is subject to change. Bitstream profiles for verification of the multimedia device software may comprise instruction mnemonics and associated operands which specify the navigation instructions in the test bitstreams. A compiler may be provided for converting the profile into bitstream field values, and a combiner may be provided for combining the bitstream field values with an existing bitstream to generate test bitstreams for verification.

Abstract: An encoded multimedia terminal having a low cost decompression circuit together with a low cost interconnect circuit coupled to a powerful server. The terminal can accept user input via a mouse, keyboard, remote control, or handset. In one embodiment, the server has ports which provide real-time audio and video encoding of source material based on user edits and the original source. An encoded bitstream is then sent to the encoded multimedia terminal for decoding. Broadly speaking, the present invention contemplates an encoded multimedia terminal comprising a microcontroller, a network interface, a multimedia bitstream decoder, and a display controller. The microcontroller receives input from a user-input device and responsively determines a user input signal. The network interface is coupled to the microcontroller to receive the user input signal and is configured to communicate the user input signal to a multitasking server which is executing a software application.

Abstract: The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design.

Abstract: A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor device stores the set of test vectors and supplies the set of vectors to the semiconductor device under the control of a first state machine generated by the hardware device. A second memory connected to the semiconductor device receives output signals from the semiconductor device in response to input test vectors. A random test iterator in the hardware engine provides a first state machine and also provides a second state machine that writes the signals output from the semiconductor device to the second memory. The test vectors are input to the semiconductor device at a rate equal to the operating rate of the semiconductor device. An expected output generator is arranged to receive the test vectors from the first memory.

Abstract: A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "modules" of the design and design hierarchy. The user can specify a level of detail to be displayed for any design element or group of design elements. Any CDFG (control and dataflow graph) object can be "annotated" with a visual attribute or with text to indicate information about the design elements represented by the object. For example, block size, interior color, border color, line thickness, line style, etc., can be used to convey quantitative or qualitative information about a CDFG object. Examples of information which can be used to "annotate" objects include power dissipation, propagation delay, the number of HDL statement represented, circuit area, number of logic gates, etc.

Abstract: A casket having a tub, lid and pedestal base each separately molded of plastic material. The tub is integrally molded of plastic as a single unit having an endless hollow peripheral side wall formed by fluid injection, the tub having curved inner and outer surfaces. The pedestal base is also integrally molded of plastic as a single unit having an endless hollow perimeter formed by fluid injection, the base having a curved upper molded surface which supportively engages with a curved bottom surface of said tub. Self aligning and locking structure for properly aligning and connecting said tub within said pedestal base is integrally molded into corresponding mating surfaces. The lid is similarly integrally molded of plastic as a single unit having an endless hollow peripheral side wall formed by fluid injection, the lid having continuous curved upper and lower surfaces. The tub and lid are hinge connected together after molding along a common longitudinal side margin therebetween.

Abstract: A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "modules" of the design and design hierarchy. The user can specify a level of detail to be displayed for any design element or group of design elements. Any CDFG (control and dataflow graph) object can be "annotated" with a visual attribute or with text to indicate information about the design elements represented by the object. For example, block size, interior color, border color, line thickness, line style, etc., can be used to convey quantitative or qualitative information about a CDFG object. Examples of information which can be used to "annotate" objects include power dissipation, propagation delay, the number of HDL statement represented, circuit area, number of logic gates, etc.

Abstract: A system for interactive, design and stimulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results, simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time.

Abstract: A general purpose architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optionally ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and microinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

Abstract: A general purposes architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optional ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and macroinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

Abstract: A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.