Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract: Methods and apparatuses, wherein the method includes providing a logic device. The method substantially surrounds a metal gate with a transition metal oxide on at least one side, wherein the transition metal oxide is comprised of hafnium oxalate and silicon dioxide. The method provides a bottom electrode (BE), wherein the BE is comprised of at least one of silicon or tungsten.

Abstract: Implementations of the technology described herein provide a Multiple Time Programmable (MTP) device, such as a Flash memory device, that implements a coupling gate in series with a floating gate. The coupling gate includes a ferroelectric capacitor and a conventional capacitor. The ferroelectric capacitor in combination with the coupling gate provides a negative capacitance such that the total capacitance of the combination of the floating gate and the coupling gate is larger than it would be if the coupling gate included only a conventional capacitor. One advantage of this device is that the effective coupling ratio between the coupling gate and the floating gate is increased. Another advantage is that the floating gate drops more voltage than conventional Multiple Time Programmable (MTP) devices.

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.