Abstract: A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

Abstract: A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

Abstract: A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

Abstract: A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.

Abstract: A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.

Abstract: An apparatus for MRI having an RF birdcage coil and an RF shield is disclosed. The RF birdcage coil includes a coil axis, an end ring portion disposed about the axis, and a plurality of legs disposed parallel to the axis and in signal communication with the end ring portion. The RF shield is disposed about the coil and is in signal communication therewith. The shield includes a cylindrical conductive sheet having first and second ends, and a plurality of sets of discontinuous slots disposed about the cylindrical sheet and running between the first and second ends, wherein a region of discontinuity within a set of the slots is aligned with the end ring portion.

Abstract: A radio frequency space cooling system (11) for a magnetic resonance imager system (10) includes a thermal energy transfer device (78). The energy transfer device (78) reduces the temperature of a cooling fluid (86) within the cooling system (11). A cooling element (82) is coupled to the energy transfer device (78) and extends along a patient bore (15) between a radio frequency shield (22) and a radio frequency coil (20) of the magnetic resonance imager system (10). The cooling element (82) has a channel (90) for passage of the cooling fluid (86).

Abstract: An imaging coil (12) includes multiple end rings (52). A center ring (53) extends parallel to and is coupled between the end rings (52). Multiple legs (86) are coupled between the end rings (52) and the center ring (53). The end rings (52) may have a first radius (R1) that is greater than a second radius (R2) of the center ring (53). The imaging coil (12) may include more than 16 legs. The imaging coil (12) may include multiple capacitor groupings (98) coupled along the end rings (52), each capacitor grouping (98) has multiple capacitors (102) with a coverage area width (W) greater than 5.0 cm. The center ring (53) may be coupled to a ground reference (110) and has low impedance such that the center ring (53) is effectively shorted to the ground reference (110).

Abstract: An integrated quadrature splitter-combiner and balun comprising: a transmission line balun operably connected to a first port and a second port; a first capacitor operably connected across the transmission line balun; a second capacitor operably connected to the first port and said balun; and a third capacitor operably connected to the second port and the balun. The second capacitor, the third capacitor, and the transmission line balun combine to form an RF splitter-combiner to split a balanced RF signal received at the first port into a first and second unbalanced quadrature RF signal transmitted at the second port and combines the first and second unbalanced quadrature RF signals received at the second port into the balanced RF signal transmitted at the first port.

Abstract: An integrated quadrature splitter-combiner and balun comprising: a transmission line balun operably connected to a first port and a second port; a first capacitor operably connected across the transmission line balun; a second capacitor operably connected to the first port and said balun; and a third capacitor operably connected to the second port and the balun. The second capacitor, the third capacitor, and the transmission line balun combine to form an RF splitter-combiner to split a balanced RF signal received at the first port into a first and second unbalanced quadrature RF signal transmitted at the second port and combines the first and second unbalanced quadrature RF signals received at the second port into the balanced RF signal transmitted at the first port.