Patents by Inventor Daniel Wilde

Daniel Wilde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967221
    Abstract: There is provided an emergency device comprising: a housing, in which the housing includes a speaker and a memory for storing an audio recording or script for guiding an end-user through an emergency. The housing has a generally cylindrical shape. The emergency device includes a single recessed button or switch located on the front face of the housing. The device is configured to play the audio recording or script via the speaker upon detection of a trigger condition, such as the button or switch being activated.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: April 23, 2024
    Assignee: ICOE TECHNOLOGY LTD.
    Inventors: Benjamin Wilde, Daniel Hook
  • Patent number: 6333746
    Abstract: A graphics system includes a graphics controller for rendering polygons with texture using an improved MIP mapping technique. The graphics controller includes a polygon engine for rendering the pixels in a polygon and a texture map engine for selecting texture elements (“texels”) from an appropriate texture map to be applied to the pixels rendered by the polygon engine. The texture map engine generates texel coordinate values from pixel coordinate values provided by the polygon engine. The appropriate texture map is selected from a set of texture maps each varying from the others by the level of detail of the texture in each map. The graphics controller selects the appropriate level of detail texture map to use to increase speed, efficiency, and realism quality of the graphics system. The determination as to which level of detail texture map is appropriate is made by computing the area bounded by adjacent texel coordinates generated by the texture map engine.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 25, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Gautam P. Vaswani, Daniel Wilde
  • Patent number: 6292191
    Abstract: Graphics software renders polygons with texture using an improved MIP mapping technique in which texels from multiple MIP maps are blended together. The software renders the pixels in a polygon and selects texture elements (“texels”) from an appropriate texture map to be applied to the pixels. The software further generates texel coordinate values to select texel values from a set of texture maps, each map varying from the others by the level of detail of the texture. The software then computes a scale factor for each texel value according an area bounded by adjacent texel coordinates. In one embodiment, vectors are defined for each the adjacent texels and the area is determined from the magnitude of the cross product of the vectors. The scale factor is then used to compute a weighted average of texels from one or more MIP maps. Further, for certain area values, no averaging occurs or, alternatively, the scale factor is set to 1.0.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: September 18, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Gautam P. Vaswani, Daniel Wilde
  • Patent number: 6052127
    Abstract: A texture value determining (TVD) circuit approximates non-homogenous 2nd order perspective texture mapping to provide texture for a polygon using linear interpolation and input parameters. The TVD circuit of the present invention includes a vertical walk subcircuit and an orthogonal walk subcircuit. The vertical walk subcircuit determines texture coordinates, u(a.sub.0,n) and v(a.sub.0,n) that represent the pixels along a vertical main slop of a triangle polygon. The orthogonal walk subcircuit determines texture coordinates, u(a.sub.m,n) and v(a.sub.m,n), for orthogonally walked polygon coordinate positions for which m>0. The orthogonally walked coordinate positions represent individual scan lines. The vertical walk subcircuit of the TVD circuit includes adders, latches, and accumulators. Each element of the vertical walk subcircuit receives a vertical main slope clock (n-clock) signal. An output of the vertical walk subsystem is computed based on the relationship,u(a.sub.0,n)=u(a.sub.0, n-1)+du.sub.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: April 18, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Gautam P. Vaswani, Michael K. Larson, Tom A. Dye, Daniel Wilde