Abstract: An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

Abstract: Link aggregation is a practice that uses multiple Ethernet links between two end points in order to obtain higher bandwidth and resiliency than possible with a single link. A flow distribution technique is provided to distribute traffic between the two end points equally across all links in the group and achieve greater efficiency. The flow distribution technique generates and sub-divides a hash value based on received packet flow. The divided portions of the hash value are used in a hierarchical fashion to select a link to use for this packet.

Abstract: Link aggregation is a practice that uses multiple Ethernet links between two end points in order to obtain higher bandwidth and resiliency than possible with a single link. A flow distribution technique is provided to distribute traffic between the two end points equally across all links in the group and achieve greater efficiency. The flow distribution technique generates and sub-divides a hash value based on received packet flow. The divided portions of the hash value are used in a hierarchical fashion to select a link to use for this packet.

Abstract: An improved computer system may include a controller including a computer processor. The system may also include a selector apparatus in communication with the controller to choose a table having a higher collision quality index than other tables under consideration by the selector apparatus. The system may further include an exchanger apparatus to configure a standby table that replaces the table chosen by the selector apparatus. The system may additionally include a switch that changes a hash function based upon the exchanger apparatus? replacement of the chosen table to enable the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller.

Abstract: Techniques are provided for hash-based routing table management in a distributed network switch. A frame having a source address and a destination address is received by a switch module having bridge elements and a routing table divided into slices of buckets, each slice having a respective property and including one or more buckets. If a routing entry for the source address is found in a first slice of a first set of buckets of the routing table responsive to a lookup request for the source address, and the property of the first slice satisfies a replication condition, then the routing entry is replicated to a second set of buckets of the routing table.

Abstract: Techniques are provided for hash-based routing table management in a distributed network switch. A frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a switch module in the distributed network switch, where the routing table is divided into slices of buckets, then routing information is determined for the source address and a routing entry is generated. The routing table is modified to include the routing entry and based on a set of hash functions and properties of the slices.

Abstract: Techniques are provided for hash-based routing table management in a distributed network switch. A frame having a source address and a destination address is received by a switch module having bridge elements and a routing table divided into slices of buckets, each slice having a respective property and including one or more buckets. If a routing entry for the source address is found in a first slice of a first set of buckets of the routing table responsive to a lookup request for the source address, and the property of the first slice satisfies a replication condition, then the routing entry is replicated to a second set of buckets of the routing table.

Abstract: Techniques are provided for hash-based routing table management in a distributed network switch. A frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a switch module in the distributed network switch, where the routing table is divided into slices of buckets, then routing information is determined for the source address and a routing entry is generated. The routing table is modified to include the routing entry and based on a set of hash functions and properties of the slices.

Abstract: Techniques are provided for hash-based routing table management in a distributed network switch. A frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a switch module in the distributed network switch, routing information is determined for the source address and a routing entry is generated. The routing table is modified to include the routing entry and based on a set of hash functions.

Abstract: Techniques are provided for hash-based routing table management in a distributed network switch. A frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a switch module in the distributed network switch, routing information is determined for the source address and a routing entry is generated. The routing table is modified to include the routing entry and based on a set of hash functions.

Abstract: Techniques are provided for cached routing table management in a distributed network switch. A frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a switch module in the distributed network switch, then routing information is determined for the source address and a routing entry is generated. The routing table is modified to include the routing entry, based on a set of hash functions. Upon accessing the generated routing entry in the modified routing table responsive to a subsequent lookup request for the source address, the set of caches is modified to include the generated routing entry.

Abstract: Techniques are provided for cached routing table management in a distributed network switch. A frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a switch module in the distributed network switch, then routing information is determined for the source address and a routing entry is generated. The routing table is modified to include the routing entry, based on a set of hash functions. Upon accessing the generated routing entry in the modified routing table responsive to a subsequent lookup request for the source address, the set of caches is modified to include the generated routing entry.

Abstract: An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

Abstract: An improved computer system may include a controller including a computer processor. The system may also include a selector apparatus in communication with the controller to choose a table having a higher collision quality index than other tables under consideration by the selector apparatus. The system may further include an exchanger apparatus to configure a standby table that replaces the table chosen by the selector apparatus. The system may additionally include a switch that changes a hash function based upon the exchanger apparatus' replacement of the chosen table to enable the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller.

Abstract: Techniques are provided for routing table synchronization for a distributed network switch. In one embodiment, a first frame having a source address and a destination address is received. If no routing entry for the source address is found in a routing table of a first switch module, routing information is determined for the source address and a routing entry is generated. An indication is sent to a second switch module, to request a routing entry for the source address to be generated in the second switch module, based on the routing information.

Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

Abstract: A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer address of an egress buffer. The respective buffer addresses of data packets received by a same source ingress adapter with a same priority level and switched through a same switching plane are linked in a same linked-list. The respective buffer addresses are preferably linked by their order of use in the egress buffer, and thus each linked-list is having a head list pointing to the oldest buffer address. The linked-lists are sorted into subsets including those linked-lists linking the respective buffer addresses of data packets received by a same source ingress adapter with a same priority level.

Abstract: A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.