Abstract: In one embodiment, an electronic system comprises a first backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the first backplane, wherein the first backplane comprises a first clock module for generating the timing signals, a second backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the second backplane, wherein the second backplane comprises a second clock module for generating the timing signals, and an electrical connector coupling the first clock module to the second clock module for communication of a timing signal, wherein the first clock module comprises a circuit for detecting the presence of the electrical connector, the first clock module providing the timing signal to an output port coupled to the electrical connector in response to the circuit, and the second clock module synchronizes to the timing signal communicated via the electrical connector.

Abstract: A redundant clock source provides a stable clock source for digital system. The clock source uses two oscillators to generate a clock signal. If one of the oscillators fails, the clock signal is generated from the other oscillator until the failed oscillator is replaced. Special filtering of the waveforms produced by the oscillators makes the clock source is resistant to jitter from the oscillators and transients that occur when an oscillator fails. This allows the clock source to not only use a redundant oscillator in an attempt to eliminate a single point of failure, but to also provide a stable clock signal even if one oscillator fails.

Abstract: In one embodiment, a clock generation system comprises first and second hot-swappable oscillator (HSO) devices that generate respective timing signals, a plurality of controllable attenuators for controllably attenuating one of the timing signals, a combiner for combining the timing signals, a redundant clock source (RCS) device for generating at least one clock for distribution to other circuits using an output of the combiner, and logic for switching which of the timing signals is attenuated in response to failure of one of the first and second HSO devices.

Abstract: In one embodiment, a clock generation system comprises a redundant clock source (RCS) device for receiving multiple timing signals and for generating at least one clock from the timing signals for distribution to other circuits, and first and second oscillator devices, wherein the RCS device switches between timing signals from the first and second oscillator devices in response to timing signal failure, wherein the RCS device filters timing signals from the first and second oscillator devices using respective bandpass filters to detect an incorrect oscillator frequency.

Abstract: In one embodiment, a clock generation system comprises first and second hot-swappable oscillator (HSO) devices that generate respective timing signals, a plurality of controllable attenuators for controllably attenuating one of the timing signals, a combiner for combining the timing signals, a redundant clock source (RCS) device for generating at least one clock for distribution to other circuits using an output of the combiner, and logic for switching which of the timing signals is attenuated in response to failure of one of the first and second HSO devices.

Abstract: In one embodiment, a clock generation system comprises a redundant clock source (RCS) device for receiving multiple timing signals and for generating at least one clock from the timing signals for distribution to other circuits, and first and second oscillator devices, wherein the RCS device switches between timing signals from the first and second oscillator devices in response to timing signal failure, wherein the RCS device filters timing signals from the first and second oscillator devices using respective bandpass filters to detect an incorrect oscillator frequency.

Abstract: In one embodiment, an electronic system comprises a first backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the first backplane, wherein the first backplane comprises a first clock module for generating the timing signals, a second backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the second backplane, wherein the second backplane comprises a second clock module for generating the timing signals, and an electrical connector coupling the first clock module to the second clock module for communication of a timing signal, wherein the first clock module comprises a circuit for detecting the presence of the electrical connector, the first clock module providing the timing signal to an output port coupled to the electrical connector in response to the circuit, and the second clock module synchronizes to the timing signal communicated via the electrical connector.

Abstract: A redundant clock source provides a stable clock source for digital system. The clock source uses two oscillators to generate a clock signal. If one of the oscillators fails, the clock signal is generated from the other oscillator until the failed oscillator is replaced. Special filtering of the waveforms produced by the oscillators makes the clock source is resistant to jitter from the oscillators and transients that occur when an oscillator fails. This allows the clock source to not only use a redundant oscillator in an attempt to eliminate a single point of failure, but to also provide a stable clock signal even if one oscillator fails.

Abstract: A short circuit protection device, which includes a comparator with a non-inverting input port, an inverting input port, and an output port, is used with first and second voltage reference signals obtained from a power supply to indicate a short-circuit condition in the power supply when the reference signals are the same. A first voltage divider is connected to the power plane of the power supply and provides the first reference signal to the non-inverting input port, and a second voltage divider is connected to the output port of the power supply and provides the second reference signal to the inverting input port, where the second reference signal is normally smaller than the first reference signal.

Abstract: A load-insensitive circuit enables a global reference clock signal source of a synchronous multiprocessor system having a plurality of nodes to be “insensitive” with respect to the insertion or removal (“hot-swap”) of a load (such as a node) when the system is operational. The load insensitive clock source is provided through the use of a customized two-way passive radio frequency power splitter having an input port and two phase-matched output ports. A high degree of isolation is provided between clock signals delivered over the output ports when the input port of the splitter is properly terminated and embedded in a controlled impedance environment. Isolation is further enhanced by terminating each output port with a constant impedance comprising a precisely-matched, 50-ohm impedance load pad.

Abstract: A dual-ported operator control panel (OCP) arrangement provides redundancy and fault tolerance capabilities in a distributed computer system. The arrangement supports the use of multiple OCPs in the computer system, which is preferably a symmetric multiprocessor (SMP) system having a management subsystem. A system control manager (SCM) microcontroller functions as a “master” of the management subsystem. One OCP functions as a primary OCP of the computer system and the others function as standby (or slave) OCPs. Two independent remote SCMs may be coupled to ports of the OCP to maintain communication between the OCP and an SCM in the event of an SCM failure. The OCP performs port arbitration to automatically select an SCM as the OCP “master” via election rules and, thereafter, only allows the elected master port control over light emitting diodes (LEDs) and a display of the OCP.

Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a novel manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

Abstract: A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules.

Abstract: An apparatus for sequencing turn-on and turn-off of power converters includes a first DC to DC converter responsive to a control signal for asserting a voltage supply signal and a sense circuit responsive to the output of said first converter to sense the level of voltage at the output of the first converter and to provide an enable signal in response to the output of said first converter when the first converter reaches a desired value. The apparatus further includes a second DC to DC converter responsive to said enable signal to provide a second supply voltage at a second different voltage level. The sequencing control has a circuit responsive to said second supply voltage and the first supply voltage, to short the second DC to DC converter to a reference potential.

Abstract: A power supply interlock technique for an electronic system which uses metal oxide semiconductor (MOS) logic circuits require two or more different supply voltages, and where each circuit board module contains its own power supplies. An open-collector enable signal is both controlled and sensed by each of the modules. The enable signal is set true when all of the supplies in the system are operating properly. However, the enable signal is set false by any one of the modules if one of the higher voltage supplies on that module is malfunctioning. The enable line also controls the lower voltage power supplies in each module. None of the lower voltage power supplies is thus permitted to operate until the enable line is set true, which occurs only when all of the modules indicate they have an operating high voltage supply available. As a result, latch-up of parasitic transistors in the circuits which drive logic signals on a system bus is avoided.

Abstract: In electronic devices, such as data processing systems that operate at high frequencies, the integrity of the interconnect or coupling apparatus transferring signals between component modules is critical to prevent compromise of information being transferred. However, the interconnect or coupling apparatus is subject to both long term and to short term impedance variations. Apparatus is disclosed for testing both the long term impedance changes and the rapid fluctuations that are not observable by current testing procedures. In addition, apparatus is disclosed for providing controllable rapid impedance changes to verify the operation of test apparatus, disclosed herein, for measuring the rapid impedance changes.

Abstract: Apparatus and method are disclosed for identifying and measuring random contact interruption events in a circuit interconnection device. A comparator circuit, adapted to be operated at high frequencies, identifies when an interrupt event has occurred. The comparator circuit, as a result of the interruption event, causes a high frequency counter circuit to count clock pulses. The count in the counter circuit is continuously applied to an RAM memory circuit, write-enabled at an addressed memory location. After the interruption event is terminated, the RAM memory circuit is no longer write enabled at the addressed location and the addressed location is changed (incremented) in preparation for the next event. The counter circuit is also reset to zero in preparation for the next interruption event. The number of counts from a clock unit having a known frequency provides the duration of the interruption event. With the use of a clock unit operated at 100 MHz, interrupt events from 10 nanoseconds to 9.