Abstract: A silicon-on-insulator radio frequency device and a silicon-on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.

Abstract: The present invention provides a sensor apparatus comprising a dielectric elastomer device, a power source, a sensor, and a processor. The dielectric elastomer device comprises a layer of dielectric material and a pair of conductive electrodes on opposing sides of the dielectric layer. The power source is coupled with the electrodes to apply a stimulus signal between the electrodes, the stimulus signal comprising two or more stimulus components of different frequencies. A sensor coupled with the electrodes obtains a sensing signal indicative of a frequency response of the dielectric elastomer device. The processor is coupled with the sensor to receive the sensing signal, and configured to detect an external coupling with the dielectric elastomer device based at least in part upon the frequency response of the dielectric elastomer device. Also provided is a method for sensing an external coupling.

Abstract: The present invention relates to pliable capacitive structures such as dielectric elastomers and similar smart materials which can be used for sensing externally applied strains which can be inferred by the determining the capacitance of the structure/material. There is provided an apparatus comprising a pliable capacitive structure for use in detecting shape or strain changes, the pliable capacitive structure having a dielectric material positioned between two electrodes; means for applying a steady-state voltage across the two electrodes; and means for determining changes in capacitance of the pliable capacitive structure using said steady state voltage.

Abstract: A silicon-on-insulator radio frequency device and a silicon-on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.

Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant.

Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant.

Abstract: A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.

Abstract: A micro-sized power source. A piezoelectric power generator, capable of harvesting energy from environmental vibration with lower level frequency, including a dielectric frame loosely containing a piezoelectric panel. The piezoelectric panel includes an electrode and a piezoelectric layer formed over an electrode and dielectric layer and an end mass formed on the piezoelectric layer. The end mass provides weight to cause the piezoelectric panel to move (vibrate) within the frame and causes the generation of electrical power.

Abstract: An axial spring balancing pin tumbler lock includes a cylindrical shell, a plug rotationally disposed within the shell and rotatable by a tubular key. The shell contains a plurality of first pin bores annularly and evenly defined to the axis of the shell for receiving first pins and first springs. The plug has a through aperture for engaging with a elongated spindle, a key bore coaxially defined on front end for receiving the tubular key, a plurality of third pin bores annularly and evenly defined on front end with same depth of the key bore for receiving third pins, and a plurality of second pin bores defined on rear end of the plug for receiving second pins and second springs. Each second pin may contacts the tubular key and one of third pins simultaneously.

Abstract: A high security cylinder lock includes a housing comprising a plurality of driver pin bores for disposing spring loaded driver pins; a plug rotatable within the housing comprising a plurality of balancing pin bores for disposing spring loaded balancing pins and a plurality of combination pin bores for disposing combination pins. Each combination pin is sandwiched between a driver pin and a balancing pin. The extension force of the balancing spring at its pre-load length is greater than the extension force of the driver spring at its fully-load length. The compound force causes at least one combination pin partially extended into a corresponding driver pin bore in the housing when the plug is at its first rotational orientation in case of no key engaged. The key profile pushes the balancing pins to move to such position that all mating surfaces of the combination pins and the driver pins to lies onto the shear line of the lock.

Abstract: An axial pin tumbler lock including a shell comprising a plurality of chambers formed in a radial pattern around a circle; a rotatable plug containing a through hole for mounting a center post, a main bore for receiving a tubular key, a first plurality of chambers formed in a radial pattern around a circle on its front end and arranged in such a way that each one of the first chambers in the plug extends coaxially with a corresponding chamber on said shell, and a second plurality of chambers formed in a radial pattern around a relatively smaller circle on its rear end, disposed in the shell; a plurality of spring-loaded driver pins disposed in the chambers on said shell; a plurality of spring loaded balance pins disposed in the second chambers and a plurality of combination pins disposed in the first chambers of said plug and initially extended into the chambers on said shell under compound extension force of the balance springs and the driver springs when the plug is at its locking position.

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

Abstract: A system and method for adjusting power consumption of a USB-based device. The system includes a power supply configured to generate a first supply voltage, a controller configured to receive the first supply voltage and generate a control signal, and a USB component configured to receive the control signal and in response operate in a first USB mode or a second USB mode. The controller is further configured to process information associated with the first supply voltage and a predetermined threshold voltage. If the first supply voltage is higher than the predetermined threshold voltage, the control signal represents a first logic state. If the first supply voltage is lower than the predetermined threshold voltage, the control signal represents a second logic state.

Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.

Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

Abstract: A planarized surface may be formed by initially forming an aperture through an insulating layer. The insulating layer and its aperture may be conformally coated with a conductive material that ultimately acts as a planarization stop. The conductive material may then be covered with another insulator that fills the remainder of the aperture. Thereafter, the structure may be planarized down to the conductive layer that acts as a planarization stop.

Abstract: A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.

Abstract: A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.