Abstract: Provided are methods for robust fault tolerant architecture, which can include methods for determining transient faults and permanent faults. Some methods described also include applying one or more fault schemes, based on the determination of transient and permanent faults. Further provided are apparatuses for robust fault tolerant architecture, which can include apparatuses having a plurality of processors and cross connectors for determining fault states. Systems and computer program products are also provided.

Abstract: Provided are methods for robust fault tolerant architecture, which can include methods for determining transient faults and permanent faults. Some methods described also include applying one or more fault schemes, based on the determination of transient and permanent faults. Further provided are apparatuses for robust fault tolerant architecture, which can include apparatuses having a plurality of processors and cross connectors for determining fault states. Systems and computer program products are also provided.

Abstract: Hypoxia plays a central role in cancer progression and resistance to therapy. A microdevice platform is engineered to recapitulate the intratumor oxygen gradients that drive the heterogeneous hypoxic landscapes in solid tumors. The microdevice design features a “tumor section”-like culture by incorporating a cell layer between two diffusion barriers, where an oxygen gradient is established by cellular metabolism and physical constraints. The oxygen gradient is confirmed by numerical simulation and imaging-based oxygen sensor measurement. Spatially-resolved hypoxic signaling in cancer cells is also demonstrated through immunostaining, gene expression assay, and hypoxia-targeted drug treatment. The microdevice platform can accurately generate and control oxygen gradients, eliminates complex microfluidic handling, allows for incorporation of additional tumor components, and is compatible with high-content imaging and high-throughput applications.

Abstract: Hypoxia plays a central role in cancer progression and resistance to therapy. A microdevice platform is engineered to recapitulate the intratumor oxygen gradients that drive the heterogeneous hypoxic landscapes in solid tumors. The microdevice design features a “tumor section”-like culture by incorporating a cell layer between two diffusion barriers, where an oxygen gradient is established by cellular metabolism and physical constraints. The oxygen gradient is confirmed by numerical simulation and imaging-based oxygen sensor measurement. Spatially-resolved hypoxic signaling in cancer cells is also demonstrated through immunostaining, gene expression assay, and hypoxia-targeted drug treatment. The microdevice platform can accurately generate and control oxygen gradients, eliminates complex microfluidic handling, allows for incorporation of additional tumor components, and is compatible with high-content imaging and high-throughput applications.

Abstract: Hypoxia plays a central role in cancer progression and resistance to therapy. A microdevice platform is engineered to recapitulate the intratumor oxygen gradients that drive the heterogeneous hypoxic landscapes in solid tumors. The microdevice design features a “tumor section”-like culture by incorporating a cell layer between two diffusion barriers, where an oxygen gradient is established by cellular metabolism and physical constraints. The oxygen gradient is confirmed by numerical simulation and imaging-based oxygen sensor measurement. Spatially-resolved hypoxic signaling in cancer cells is also demonstrated through immunostaining, gene expression assay, and hypoxia-targeted drug treatment. The microdevice platform can accurately generate and control oxygen gradients, eliminates complex microfluidic handling, allows for incorporation of additional tumor components, and is compatible with high-content imaging and high-throughput applications.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: A method of fabricating an ultra-small semiconductor structure comprising the following steps. A substrate having a lower dielectric layer and an overlying upper dielectric layer formed thereover is provided. Using a lithography process having a lithography limit, the upper dielectric layer is patterned to form a first opening exposing a portion of the lower dielectric layer. The first opening having exposed side walls and a width equal to the lithography limit. Sidewall spacers having a lower width are formed over the exposed side walls of the first opening. Using the sidewall spacers as masks, the lower dielectric layer is patterned to form a lower opening having a width less than the first opening width. The patterned upper dielectric layer is removed. An ultra-small semiconductor structure is formed within the lower opening. The ultra-small semiconductor structure having a width equal to the lithography limit minus twice the lower width of the sidewall spacer.

Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer.

Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: A method for forming a high aspect ratio via. In one embodiment, the present method comprises providing a first material into which a high aspect ratio via is to be formed. The present embodiment then deposits a first layer of a second material above the first material. Next, the present method recites forming an opening in the first layer of the second material. A second layer of the second material is then deposited above the first layer of the second material and into the opening formed into the first layer of the second material. The present embodiment then etches the second layer of the second material such that the opening extends through the second layer of the second material and through the first layer of the second material. In so doing, the opening is configured to have a profile conducive to the adherence of overlying material thereto.

Abstract: A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.

Abstract: A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target.

Abstract: A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.