Abstract: In general, embodiments of the invention relate to a method for capturing video frames. The method includes obtaining a depth-data frame of an environment using a depth-sensing camera and an infrared illuminator, where the environment is illuminated by an illumination pattern emitted by the infrared illuminator, obtaining, an infrared illuminator parameterization for the illumination pattern emitted by the infrared illuminator, obtaining a desired frame exposure time, based on a desired frame exposure, determining, based on the infrared illuminator parameterization and the desired frame exposure time, an actual frame exposure time, and after determining the actual frame exposure time, obtaining a frame of the environment using the actual frame exposure time using the infrared illuminator with the illumination pattern.

Abstract: ORing diodes are used for power redundancy. In order to reduce the power loss due to the diode forward drop voltage, active ORing power MOSFETs are proposed to replace the diodes. With the active ORing controller and power MOSFETs, the power loss can be easily decreased by 90%. To make an N-channel MOSFET work like a diode when it is in reverse and have a very small forward voltage drop when it is in forward, an ORing controller is provided. Its offset, hysteresis, and propagation delay times are optimized for speed, stability, and noise immunity. Its ORing function is tested in an ORing demo board. Its FET check feature makes a live checkup of the ORing power MOSFETs to improve the reliability of the redundant power system.

Abstract: ORing diodes are used for power redundancy. In order to reduce the power loss due to the diode forward drop voltage, active ORing power MOSFETs are proposed to replace the diodes. With the active ORing controller and power MOSFETs, the power loss can be easily decreased by 90%. To make an N-channel MOSFET work like a diode when it is in reverse and have a very small forward voltage drop when it is in forward, an ORing controller is provided. Its offset, hysteresis, and propagation delay times are optimized for speed, stability, and noise immunity. Its ORing function is tested in an ORing demo board. Its FET check feature makes a live checkup of the ORing power MOSFETs to improve the reliability of the redundant power system.

Abstract: A voltage reference circuit includes a band-gap reference circuit for providing a reference voltage and having breakpoint compensation to adjust the temperature coefficient of the reference voltage as a function of temperature. A thermal limit transistor biased by a voltage having a positive temperature coefficient begins conducting when the operating temperature reaches a predetermined value to provide a compensation current. The compensation current is added to the collector current flowing into one of a pair of transistors within the band-gap reference circuit, and a current controlled current source responds to an increase in collector current in the other one of the pair of transistors by making the collector currents flowing into both transistors equal. This increases the voltage drop across a pair of resistors to increase a band-gap voltage across a portion of an output divider network, to in turn increase the reference voltage provided across the entire divider network.

Abstract: A voltage reference circuit employs a bandgap cell to establish a voltage reference, stabilized relative to the bandgap voltage of silicon, and a compensation circuit for compensating non-linear temperature dependence of the bandgap stabilized voltage reference. A two or three transistor type bandgap cell may be employed to establish the bandgap reference voltage along with a voltage divider network to adjust the output reference voltage relative to the bandgap voltage of silicon. The compensation circuit preferably employs a compensation resistor in the resistor divider network, and a switching circuit for switching current therethrough. This provides empirically determined adjustments to the output reference voltage by switching current through the compensation resistor in accordance with predetermined temperature thresholds.

Abstract: A logic array includes multiple gated current sources for receiving respective logic input signals, each of the gated current sources is coupled to a respective pair of row conductors and sends current to one row conductor or the other of that pair to indicate the state of the received input signal, column conductors are coupled to selectively receive current from any of the row conductors, a circuit generates respective NAND signals indicating when current is received by the column conductors; additional gated current sources respectively receive the NAND signals and send current to respective additional row conductors when the received signals are in predetermined states, additional column conductors selectively receive current from the additional row conductors, and an output circuit is coupled to the additional column conductors for generating respective output NAND signals indicating when current is received therefrom.

Abstract: A logic array includes a plurality of gated current sources which receive respective input signals, each of said gated current sources is coupled to a respective row conductor and sends current to that row conductor when the received input signal is in a predetermined state; the respective row conductors are partitioned into several groups; a respective high capacitance column conductor is provided for each group; within each group, diodes selectively couple current from the row conductors to the respective high capacitance column conductor; a low capacitance column conductor is provided; and a circuit generates current on the low capacitance column conductor representing the logical NAND of selected input signals when current is coupled from any group of row conductors to the high capacitance column conductor for that group.