Abstract: Various examples are directed to systems and methods involving a managed NAND non-volatile memory device comprising a memory array and a memory controller. The memory controller may receive a verification request from a requesting device, the verification request comprising an indication of a first portion of the memory array, and a first known check value. The memory controller may apply an operation based at least in part on first data from the first portion of the memory array to generate a calculated check value and determine verification result data based at least in part on the first known check value and the calculated check value.

Abstract: In some implementations, a memory device may include a memory and a controller. The controller may receive, from a host device, a read-verify command. The controller may obtain, from the memory, a chunk of data based on the read-verify command. The controller may verify, based on the read-verify command, the chunk of data without transferring the chunk of data to the host device. The controller may provide, to the host device, an indication of a pass-fail status of the chunk of data based on the verification of the chunk of data.

Abstract: A memory device includes a memory array and a memory control unit. The memory array includes memory cells. The memory control unit is configured to calculate an amount of data that can be written by a host device to the memory device in a burst performance mode before changing to sustained performance mode; calculate an amount of data that can be written to the memory device in the sustained performance mode before changing to writing the memory according to a dirty performance mode; and provide results of the calculations to the host device.

Abstract: A system includes a memory device; and a processing device, operatively coupled with the memory device, to perform operations including exposing, to a host system, a plurality of values of an overprovisioning parameter of the memory device; receiving, from the host system, a selection of value of the plurality of values; and updating, based on the selection, a value of an operating parameter specifying an overprovisioned capacity of the memory device.

Abstract: Various examples are directed to systems and methods involving a managed NAND non-volatile memory device comprising a memory array and a memory controller. The memory controller may receive a verification request from a requesting device, the verification request comprising an indication of a first portion of the memory array, and a first known check value. The memory controller may apply an operation based at least in part on first data from the first portion of the memory array to generate a calculated check value and determine verification result data based at least in part on the first known check value and the calculated check value.

Abstract: A memory device includes a memory array and a memory control unit. The memory array includes memory cells. The memory control unit is configured to calculate an amount of data that can be written by a host device to the memory device in a burst performance mode before changing to sustained performance mode; calculate an amount of data that can be written to the memory device in the sustained performance mode before changing to writing the memory according to a dirty performance mode; and provide results of the calculations to the host device.

Abstract: In some implementations, a memory device may include a memory and a controller. The controller may receive, from a host device, a read-verify command. The controller may obtain, from the memory, a chunk of data based on the read-verify command. The controller may verify, based on the read-verify command, the chunk of data without transferring the chunk of data to the host device. The controller may provide, to the host device, an indication of a pass-fail status of the chunk of data based on the verification of the chunk of data.

Abstract: Methods, systems, and devices for techniques for efficient memory system programming are described. A memory system may operate in a programming mode to be programmed with data at various stages of being implemented into a system. In some examples, the memory system may write data according to a programming command sequence, including a first command indicating multiple logical block address (LBA) ranges of the memory system. The memory system may receive multiple second commands that each include data associated with respective LBA ranges and may write, for each respective LBA range, data to physical addresses of the memory system. Alternatively, the memory system may write a value to a register indicating a total quantity of LBAs associated with writing data while operating in the programming mode. The memory system may decrement the value of the register in response to writing data to the memory system.

Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.