Abstract: A modular hub driver architecture may include a multi-delay block configured to provide an enhanced delay match among N distinct stages of a distributed modulating electro-optical interface core. The electro-optical multi-core modulator driver may include an input impedance matching stage and a pre-conditioning circuit configured to generate a number M, an integer divisor of N, of delayed replicas of an electrical modulating signal. The electro-optical multi-core modulator may include an array of M launch buffers of the replica signals, and an array of M multi-delay blocks, each including delay circuit modules differently cascaded on distinct signal paths, and configured to receive, at respective inputs, the M replica signals and to output N/M differently delayed replicas of the input signals, each driving a correspondent output stage of one on the N electro-optical interface cores.

Abstract: A differential or pseudo-differential TIA includes an auxiliary differential amplifier input transistor pair cross-coupled to the output nodes to cancel undesired output signal components. The advantages of a classical differential topology are retained while performance at a high data rate is significantly improved.

Abstract: A modular hub driver architecture may include a multi-delay block configured to provide an enhanced delay match among N distinct stages of a distributed modulating electro-optical interface core. The electro-optical multi-core modulator driver may include an input impedance matching stage and a pre-conditioning circuit configured to generate a number M, an integer divisor of N, of delayed replicas of an electrical modulating signal. The electro-optical multi-core modulator may include an array of M launch buffers of the replica signals, and an array of M multi-delay blocks, each including delay circuit modules differently cascaded on distinct signal paths, and configured to receive, at respective inputs, the M replica signals and to output N/M differently delayed replicas of the input signals, each driving a correspondent output stage of one on the N electro-optical interface cores.

Abstract: A differential or pseudo-differential TIA includes an auxiliary differential amplifier input transistor pair cross-coupled to the output nodes to cancel undesired output signal components. The advantages of a classical differential topology are retained while performance at a high data rate is significantly improved.

Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.

Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.